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Serial Peripheral Interface Module (SPI)
16.8.2 Mode Fault Error
Technical Data
294
BYTE 1
SPI RECEIVE
1
COMPLETE
SPRF
OVRF
READ
2
SPSCR
READ
3
SPDR
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
3
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
5
BYTE 2 SETS SPRF BIT.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
Figure 16-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
Setting the SPMSTR bit selects master mode and configures the
SPSCK and MOSI pins as outputs and the MISO pin as an input.
Clearing SPMSTR selects slave mode and configures the SPSCK and
MOSI pins as inputs and the MISO pin as an output. The mode fault bit,
MODF, becomes set any time the state of the slave select pin, SS, is
inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault
error occurs if:
•
The SS pin of a slave SPI goes high during a transmission
•
The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.
Serial Peripheral Interface Module (SPI)
BYTE 2
BYTE 3
5
7
4
6
8
8
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
11
BYTE 4 SETS SPRF BIT.
12
CPU READS SPSCR.
13
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
14
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
MC68HC908AB32
BYTE 4
11
9
12
14
10
13
Rev. 1.0
—
MOTOROLA
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