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Timer Interface Module A (TIMA)
NOTE:
Technical Data
190
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0 and TIMA channel 2 status
and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1B to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3B to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation.
See
Table
11-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TBCHx pin. See
1 = Initial output level low
0 = Initial output level high
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMA status and control register
(TASC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to the port I/O, and pin TACHx is available as a general-purpose I/O
pin.
Table 11-3
shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Timer Interface Module A (TIMA)
Table
11-3. Reset clears the MSxA bit.
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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