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System Integration Module (SIM)
8.5.1 SIM Counter during Power-On Reset
8.5.2 SIM Counter during Stop Mode Recovery
8.5.3 SIM Counter and Reset States
8.6 Exception Control
Technical Data
118
The power-on reset (POR) module detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
The SIM counter is also used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short STOP recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a logic 1, then
the stop recovery is reduced from the normal delay of 4096 CGMXCLK
cycles down to 32 CGMXCLK cycles. This is ideal for applications using
canned oscillators that do not require long start-up times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared.
External reset has no effect on the SIM counter. (See
for details.) The SIM counter is free-running after all reset states. (See
8.4.2 Active Resets from Internal Sources
internal reset recovery sequences.)
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
System Integration Module (SIM)
8.7.2 Stop Mode
for counter control and
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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