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Source
Form
CMP # opr
CMP opr
CMP opr
CMP opr ,X
Compare A with M
CMP opr ,X
CMP ,X
CMP opr ,SP
CMP opr ,SP
COM opr
COMA
COMX
Complement (One's Complement)
COM opr ,X
COM ,X
COM opr ,SP
CPHX # opr
Compare H:X with M
CPHX opr
CPX # opr
CPX opr
CPX opr
CPX ,X
Compare X with M
CPX opr ,X
CPX opr ,X
CPX opr ,SP
CPX opr ,SP
DAA
Decimal Adjust A
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr, X ,rel
DBNZ X ,rel
DBNZ opr, SP ,rel
DEC opr
DECA
DECX
Decrement
DEC opr ,X
DEC ,X
DEC opr ,SP
DIV
Divide
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Table 7-1. Instruction Set Summary (Continued)
Operation
A ← (A) – 1 or M ← (M) – 1 or X ← (X) –
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
Central Processor Unit (CPU)
Description
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(H:X) – (M:M + 1)
(X) – (M)
(A)
10
1
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
Central Processor Unit (CPU)
Effect on
CCR
V H I N Z C
IMM
DIR
EXT
IX2
– –
IX1
IX
SP1
SP2
DIR
INH
INH
0 – –
1
IX1
IX
SP1
IMM
– –
DIR
IMM
DIR
EXT
IX2
– –
IX1
IX
SP1
SP2
U – –
INH
DIR
INH
– – – – – –
INH
IX1
IX
SP1
DIR
INH
INH
– –
–
IX1
IX
SP1
– – – –
INH
Opcode Map
A1
ii
2
B1
dd
3
C1
hh ll
4
D1
ee ff
4
E1
ff
3
F1
2
9EE1
ff
4
9ED1
ee ff
5
33
dd
4
43
1
53
1
63
ff
4
73
3
9E63
ff
5
65
ii ii+1
3
75
dd
4
A3
ii
2
B3
dd
3
C3
hh ll
4
D3
ee ff
4
E3
ff
3
F3
2
9EE3
ff
4
9ED3
ee ff
5
72
2
5
3B
dd rr
3
4B
rr
3
5B
rr
5
6B
ff rr
4
7B
rr
6
9E6B
ff rr
3A
dd
4
4A
1
5A
1
6A
ff
4
7A
3
9E6A
ff
5
52
7
Technical Data
101
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