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;
This code works if the H register has been pushed onto the stack in the break
;
service routine software. This code should be executed at the end of the break
;
service routine software.
HIBYTE
EQU
LOBYTE
EQU
;
If not SBSW, do RTI
BRCLR
TST
BNE
DEC
DOLO
DEC
RETURN
PULH
RTI
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Address:
$FE00
Bit 7
Read:
R
Write:
Reset:
0
Note: Writing a logic 0 clears SBSW.
Figure 22-6. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example.
5
6
SBSW,SBSR, RETURN
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
Break Module (BRK)
6
5
4
R
R
R
0
0
0
R
= Reserved
;
See if wait mode or stop mode was exited by
;
break.
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
Break Module (BRK)
Break Module Registers
3
2
1
SBSW
R
R
Note
0
0
0
Technical Data
Bit 0
R
0
371
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