Table 1-13. Ipic Memory Map-Control And Status Registers - Motorola MVME162LX 300 Series Installation And Use Manual

Board Level Hardware Description
1
Table 1-13. IPIC Memory Map—Control and Status Registers
Register
Offset
$00 CHIP ID
$01 CHIP REVISION
$02 RESERVED
$03 RESERVED
$04 IP_a MEM BASE
UPPER
$05 IP_a MEM BASE
LOWER
$06 IP_b MEM BASE
UPPER
$07 IP_b MEM BASE
LOWER
$08 IP_c MEM BASE
UPPER
$09 IP_c MEM BASE
LOWER
$0A IP_d MEM BASE
UPPER
$0B IP_d MEM BASE
LOWER
$0C IP_a MEM SIZE
$0D IP_b MEM SIZE
$0E IP_c MEM SIZE
$0F IP_d MEM SIZE
$10 IP_a INT0 CONTROL
$11 IP_a INT1 CONTROL
$12 IP_b INT0 CONTROL
$13 IP_b INT1 CONTROL
1-42
Table 1-13 contains a summary of the IPIC CSR registers. The CSR
registers can be accessed as bytes, words, or longwords; they should not be
accessed as lines. They are shown in the table as bytes.
IPIC Base Address = $FFFBC000
Register
Name
D7
0
0
0
0
a_BASE31 a_BASE30 a_BASE29 a_BASE28 a_BASE27 a_BASE26 a_BASE25 a_BASE24
a_BASE23 a_BASE22 a_BASE21 a_BASE20 a_BASE19 a_BASE18 a_BASE17 a_BASE16
b_BASE31 b_BASE30 b_BASE29 b_BASE28 b_BASE27 b_BASE26 b_BASE25 b_BASE24
b_BASE23 b_BASE22 b_BASE21 b_BASE20 b_BASE19 b_BASE18 b_BASE17 b_BASE16
c_BASE31 c_BASE30 c_BASE29 c_BASE28 c_BASE27 c_BASE26 c_BASE25 c_BASE24
c_BASE23 c_BASE22 c_BASE21 c_BASE20 c_BASE19 c_BASE18 c_BASE17 c_BASE16
d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24
d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19 d_BASE18 d_BASE17 d_BASE16
a_SIZE23 a_SIZE22
b_SIZE23 b_SIZE22
c_SIZE23 c_SIZE22
d_SIZE23 d_SIZE22
a0_PLTY a0_E/L*
a1_PLTY a1_E/L*
b0_PLTY b0_E/L*
b1_PLTY b1_E/L*
Register Bit Names
D6 D5 D4
0 1 0
0 0 0
0 0 0
0 0 0
a_SIZE21 a_SIZE20
b_SIZE21 b_SIZE20
c_SIZE21 c_SIZE20
d_SIZE21 d_SIZE20
a0_INT a0_IEN
a1_INT a1_IEN
b0_INT b0_IEN
b1_INT b1_IEN
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D3 D2 D1
0 0 1
0 0 0
0 0 0
0 0 0
a_SIZE19 a_SIZE18 a_SIZE17
b_SIZE19 b_SIZE18 b_SIZE17
c_SIZE19 c_SIZE18 c_SIZE17
d_SIZE19 d_SIZE18 d_SIZE17
a0_ICLR a0_IL2 a0_IL1
a1_ICLR a1_IL2 a1_IL1
b0_ICLR b0_IL2 b0_IL1
b1_ICLR b1_IL2 b1_IL1
D0
1
0
0
0
a_SIZE16
b_SIZE16
c_SIZE16
d_SIZE16
a0_IL0
a1_IL0
b0_IL0
b1_IL0