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MC68HC908AB32
Rev. 1.0
—
MOTOROLA
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode is used also to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See
9.6.2 PLL Bandwidth Control Register
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL start-up, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. See
Circuit. If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See
9.7 Interrupts
The following conditions apply when the PLL is in automatic bandwidth
control mode:
•
The ACQ bit (see
(PBWC)) is a read-only indicator of the mode of the filter. (See
9.4.2.2 Acquisition and Tracking
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance ∆
TRK
certain tolerance ∆
Specifications)
•
The LOCK bit is a read-only indicator of the locked state of the
PLL.
•
The LOCK bit is set when the VCO frequency is within a certain
tolerance ∆
LOCK
a certain tolerance ∆
Specifications)
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's
lock condition changes, toggling the LOCK bit. (See
Control Register
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below f
Clock Generator Module (CGM)
for information and precautions on using interrupts).
9.6.2 PLL Bandwidth Control Register
and is cleared when the VCO frequency is out of a
. (See
9.10 Acquisition/Lock Time
UNT
and is cleared when the VCO frequency is out of
. (See
9.10 Acquisition/Lock Time
UNL
(PCTL))
Clock Generator Module (CGM)
Functional Description
(PBWC). If PLL
9.4.3 Base Clock Selector
Modes)
9.6.1 PLL
Technical Data
BUSMAX
137
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