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Configuration Register (CONFIG)
6.5 Configuration Register 2
Technical Data
88
Address:
$003F
Bit 7
6
Read:
R
EEDIVCLK
Write:
Reset:
0
R
= Reserved
Figure 6-2. Configuration Register 2 (CONFIG2)
EEDIVCLK — EEPROM Timebase Divider Clock Select Bit
EEDIVCLK selects the reference clock source for the EEPROM
timebase divider. (See
1 = CPU bus clock drives the EEPROM timebase divider
0 = CGMXCLK drives the EEPROM timebase divider
Extra care should be exercised when using this emulation part for
development of code to be run in ROM AB, AS or AZ parts that the
options selected by setting the CONFIG2 register match exactly the
options selected on any ROM code request submitted. The
enable/disable logic is not necessarily identical in all parts of the
AB, AS, and AZ families. If in doubt, check with your local field
applications representative.
Configuration Register (CONFIG)
5
4
3
R
R
R
Section 5.
EEPROM.)
MC68HC908AB32
2
1
Bit 0
R
R
R
Rev. 1.0
—
MOTOROLA
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