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Timer Interface Module A (TIMA)
Addr.
Register Name
Timer A Channel 1
$002B
Register Low
(TACH1L)
Timer A Channel 2 Status
$002C
and Control Register
(TASC2)
Timer A Channel 2
$002D
Register High
(TACH2H)
Timer A Channel 2
$002E
Register Low
(TACH2L)
Timer A Channel 3 Status
$002F
and Control Register
(TASC3)
Timer A Channel 3
$0030
Register High
(TACH3H)
Timer A Channel 3
$0031
Register Low
(TACH3L)
Figure 11-2. TIMA I/O Register Summary (Sheet 2 of 2)
11.5.2 Input Capture
Technical Data
174
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
Read:
CH2F
CH2IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
Read:
Bit 7
6
Write:
Reset:
Read:
CH3F
CH3IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
Read:
Bit 7
6
Write:
Reset:
= Unimplemented
With the input capture function, the TIMA can capture the time at which
an external event occurs. When an active edge occurs on the pin of an
input capture channel, the TIMA latches the contents of the TIMA
counter into the TIMA channel registers, TACHxH:TACHxL. The polarity
of the active edge is programmable. Input captures can generate
TIMA CPU interrupt requests.
Timer Interface Module A (TIMA)
5
4
3
5
4
3
Indeterminate after reset
MS2B
MS2A
ELS2B
0
0
0
13
12
11
Indeterminate after reset
5
4
3
Indeterminate after reset
0
MS3A
ELS3B
0
0
0
13
12
11
Indeterminate after reset
5
4
3
Indeterminate after reset
2
1
Bit 0
2
1
Bit 0
ELS2A
TOV2
CH2MAX
0
0
0
10
9
Bit 8
2
1
Bit 0
ELS3A
TOV3
CH3MAX
0
0
0
10
9
Bit 8
2
1
Bit 0
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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