Motorola MC68HC908AB32 Technical Data Manual page 104

Central Processor Unit (CPU)
Source
Operation
Form
ROR opr
RORA
RORX
Rotate Right through Carry
ROR opr ,X
ROR ,X
ROR opr ,SP
RSP Reset Stack Pointer
RTI Return from Interrupt
RTS Return from Subroutine
SBC # opr
SBC opr
SBC opr
SBC opr ,X
Subtract with Carry
SBC opr ,X
SBC ,X
SBC opr ,SP
SBC opr ,SP
SEC Set Carry Bit
SEI Set Interrupt Mask
STA opr
STA opr
STA opr ,X
STA opr ,X Store A in M
STA ,X
STA opr ,SP
STA opr ,SP
STHX opr Store H:X in M
STOP Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr ,X
STX opr ,X Store X in M
STX ,X
STX opr ,SP
STX opr ,SP
Technical Data
104
Table 7-1. Instruction Set Summary (Continued)
b7
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
A ← (A) – (M) – (C)
(M:M + 1) ← (H:X)
I ← 0; Stop Oscillator
Central Processor Unit (CPU)
Effect on
CCR
Description
V H I N Z C
C
– –
b0
SP ← $FF
– – – – – – INH
– – – – – – INH
– –
C ← 1
– – – – – 1 INH
I ← 1
– – 1 – – – INH
M ← (A)
0 – –
0 – –
– – 0 – – – INH
M ← (X)
0 – –
DIR 36 dd
INH 46
INH 56
IX1 66 ff
IX 76
SP1 9E66 ff
9C
INH 80
81
IMM A2 ii
DIR B2 dd
EXT C2 hh ll
IX2 D2 ee ff
IX1 E2 ff
IX F2
SP1 9EE2 ff
SP2 9ED2 ee ff
99
9B
DIR B7 dd
EXT C7 hh ll
IX2 D7 ee ff
– IX1 E7 ff
IX F7
SP1 9EE7 ff
SP2 9ED7 ee ff
– DIR 35 dd
8E
DIR BF dd
EXT CF hh ll
IX2 DF ee ff
– IX1 EF ff
IX FF
SP1 9EEF ff
SP2 9EDF ee ff
MC68HC908AB32 Rev. 1.0
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MOTOROLA
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