Stop Mode Entry Timing - Motorola MC68HC908AB32 Technical Data Manual

System Integration Module (SIM)
CGMXCLK
INT/BREAK
IAB
Figure 8-16. Stop Mode Recovery from Interrupt or Break
Technical Data
126
A break interrupt during stop mode sets the SIM break STOP/WAIT bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 8-15
CPUSTOP
IAB STOP ADDR
IDB PREVIOUS DATA
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 8-15. Stop Mode Entry Timing
STOP RECOVERY PERIOD
STOP +1 STOP + 2
System Integration Module (SIM)
shows stop mode entry timing.
STOP ADDR + 1 SAME
NEXT OPCODE
STOP + 2 SP SP – 1
MC68HC908AB32
SAME
SAME SAME
SP – 2 SP – 3
Rev. 1.0
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MOTOROLA