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9.10.4 Reaction Time Calculation
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
•
Correct selection of filter capacitor, C
(see
9.10.3 Choosing a Filter
•
Room temperature operation
•
Negligible external leakage on CGMXFC
•
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K
is the K factor when the PLL is configured in acquisition mode, and
ACQ
K
is the K factor when the PLL is configured in tracking mode. See
TRK
9.4.2.2 Acquisition and Tracking
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode the acquisition and lock times are
quantized into units based on the reference frequency. See
Manual and Automatic PLL Bandwidth
clock cycles, n
, is required to ascertain whether the PLL is within the
ACQ
tracking mode entry tolerance ∆
Also, a certain number of clock cycles, n
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
Capacitor)
Modes.
V
8
DDA
t
=
------------ -
------------ -
ACQ
f
K
RDV
ACQ
V
4
DDA
t
=
------------ -
------------
AL
f
K
RDV
TRK
t
=
t
+
t
LOCK
ACQ
AL
Modes. A certain number of
, before exiting acquisition mode.
TRK
TRK
Clock Generator Module (CGM)
,
F
9.4.2.3
, is required to ascertain
Technical Data
155
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