Instruction Set Summary - Motorola MC68HC908AB32 Technical Data Manual

Central Processor Unit (CPU)
Source
Operation
Form
ADC # opr
ADC opr
ADC opr
ADC opr ,X
Add with Carry
ADC opr ,X
ADC ,X
ADC opr ,SP
ADC opr ,SP
ADD # opr
ADD opr
ADD opr
ADD opr ,X
Add without Carry
ADD opr ,X
ADD ,X
ADD opr ,SP
ADD opr ,SP
AIS # opr
Add Immediate Value (Signed) to SP
AIX # opr
Add Immediate Value (Signed) to H:X
AND # opr
AND opr
AND opr
AND opr ,X
Logical AND
AND opr ,X
AND ,X
AND opr ,SP
AND opr ,SP
ASL opr
ASLA
ASLX Arithmetic Shift Left
ASL opr ,X
(Same as LSL)
ASL ,X
ASL opr ,SP
ASR opr
ASRA
ASRX
Arithmetic Shift Right
ASR opr ,X
ASR opr ,X
ASR opr ,SP
BCC rel Branch if Carry Bit Clear
BCLR n , opr
Clear Bit n in M
Technical Data
98
Table 7-1. Instruction Set Summary
Description
A ← (A) + (M) + (C)
A ← (A) + (M)
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
A ← (A) & (M)
C
b7
b7
PC ← (PC) + 2 + rel ? (C) = 0
Mn ← 0
Central Processor Unit (CPU)
Effect on
CCR
V H I N Z C
–
–
– – – – – – IMM
– – – – – – IMM
0 – – –
– –
0
b0
C
– –
b0
– – – – – – REL
– – – – – –
MC68HC908AB32
IMM A9 ii 2
DIR B9 dd 3
EXT C9 hh ll 4
IX2 D9 ee ff 4
IX1 E9 ff 3
IX F9 2
SP1 9EE9 ff 4
SP2 9ED9 ee ff 5
IMM AB ii 2
DIR BB dd 3
EXT CB hh ll 4
IX2 DB ee ff 4
IX1 EB ff 3
IX FB 2
SP1 9EEB ff 4
SP2 9EDB ee ff 5
A7 ii 2
AF ii 2
IMM A4 ii 2
DIR B4 dd 3
EXT C4 hh ll 4
IX2 D4 ee ff 4
IX1 E4 ff 3
IX F4 2
SP1 9EE4 ff 4
SP2 9ED4 ee ff 5
DIR 38 dd 4
INH 48 1
INH 58 1
IX1 68 ff 4
IX 78 3
SP1 9E68 ff 5
DIR 37 dd 4
INH 47 1
INH 57 1
IX1 67 ff 4
IX 77 3
SP1 9E67 ff 5
24 rr 3
DIR (b0) 11 dd 4
DIR (b1) 13 dd 4
DIR (b2) 15 dd 4
DIR (b3) 17 dd 4
DIR (b4) 19 dd 4
DIR (b5) 1B dd 4
DIR (b6) 1D dd 4
DIR (b7) 1F dd 4
Rev. 1.0
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MOTOROLA