Signal Naming Conventions; Sim Block Diagram - Motorola MC68HC908AB32 Technical Data Manual

RESET
PIN LOGIC
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
MC68HC908AB32 Rev. 1.0
—
MOTOROLA
STOP/WAIT
CONTROL
CLOCK
CLOCK GENERATORS
CONTROL
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 8-1. SIM Block Diagram
Table 8-1. Signal naming conventions
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
System Integration Module (SIM)
SIM
COUNTER
÷
2
MASTER
RESET
CONTROL
RESET
Description
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
Introduction
Technical Data
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