Mode, Edge, And Level Selection - Motorola MC68HC908AB32 Technical Data Manual

NOTE:
NOTE:
MC68HC908AB32 Rev. 1.0
—
MOTOROLA
Table 11-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB
X 0
X 1
0 0
0 0
0 0
0 1
0 1
0 1
1 X
1 X
1 X
Before enabling a TIMA channel register for input capture operation,
make sure that the TACHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMA counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic zero, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 11-13 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
Timer Interface Module A (TIMA)
ELSxA Mode
0 0
Output
Preset
0 0
0 1
Input
1 0
Capture
1 1
0 1
Output
1 0 Compare
or PWM
1 1
0 1 Buffered
Output
1 0
Compare or
Buffered
1 1
PWM
Timer Interface Module A (TIMA)
I/O Registers
Configuration
Pin under Port Control;
Initial Output Level High
Pin under Port Control;
Initial Output Level Low
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Technical Data
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