Spi Master Timing - Motorola MC68HC908AB32 Technical Data Manual

SS
INPUT
SPSCK OUTPUT
NOTE
CPOL = 0
SPSCK OUTPUT
NOTE
CPOL = 1
MISO
INPUT
MOSI
OUTPUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
SS
INPUT
SPSCK OUTPUT
CPOL = 0
SPSCK OUTPUT
CPOL = 1
MISO
INPUT
10
MOSI
OUTPUT
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
MC68HC908AB32 Rev. 1.0
—
MOTOROLA
SS PIN OF MASTER HELD HIGH
4
5
MSB IN
11
MASTER MSB OUT
a) SPI Master Timing (CPHA = 0)
SS PIN OF MASTER HELD HIGH
1
5
4
5
4
MSB IN
11
MASTER MSB OUT
b) SPI Master Timing (CPHA = 1)
Figure 23-1. SPI Master Timing
Electrical Specifications
1
5
4
BITS 6–1
10
BITS 6–1
BITS 6–1
10
BITS 6–1
Electrical Specifications
SPI Characteristics
6 7
LSB IN
11
MASTER LSB OUT
NOTE
NOTE
6 7
LSB IN
MASTER LSB OUT
Technical Data
381