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Alternative Function:
17.9.2 Data Direction Register G (DDRG)
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Address:
$000A
Bit 7
6
Read:
0
0
Write:
Reset:
Figure 17-22. Port G Data Register (PTG)
PTG[2:0] — Port G Data Bits
These read/write bits are software programmable. Data direction of
each port G pin is under the control of the corresponding bit in data
direction register G. Reset has no effect on port G data.
KBD[2:0] — The keyboard interrupt enable bits, KBIE[2:0], in the
keyboard interrupt enable register (KBIER), enable the port G pins as
external interrupt pins. See
(KBI).
Data direction register G determines whether each port G pin is an input
or an output. Writing logic 1 to a DDRG bit enables the output buffer for
the corresponding port G pin; a logic 0 disables the output buffer.
Address:
$000E
Bit 7
6
Read:
0
0
Write:
Reset:
0
0
Figure 17-23. Data Direction Register G (DDRG)
Input/Output (I/O) Ports
5
4
3
0
0
0
Unaffected by reset
Section 19. Keyboard Interrupt Module
5
4
3
0
0
0
0
0
0
Input/Output (I/O) Ports
Port G
2
1
Bit 0
PTG2
PTG1
PTG0
KBD2
KBD1
KBD0
2
1
Bit 0
DDRG2
DDRG1
DDRG0
0
0
0
Technical Data
333
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