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Clock Generator Module (CGM)
Addr.
Register Name
PLL Control Register
$001C
(PCTL)
PLL Bandwidth Control
$001D
Register
(PBWC)
PLL Programming
$001E
Register
(PPG)
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
9.6.1 PLL Control Register (PCTL)
Technical Data
144
Bit 7
6
Read:
PLLF
PLLIE
Write:
Reset:
0
0
Read:
LOCK
AUTO
Write:
Reset:
0
0
Read:
MUL7
MUL6
Write:
Reset:
0
1
= Unimplemented
Figure 9-4. CGM I/O Register Summary
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address:
$001C
Bit 7
6
Read:
PLLF
PLLIE
Write:
Reset:
0
0
= Unimplemented
Figure 9-5. PLL Control Register (PCTL)
Clock Generator Module (CGM)
5
4
3
1
PLLON
BCS
1
0
1
0
ACQ
XLD
0
0
0
MUL5
MUL4
VRS7
1
0
0
5
4
3
1
PLLON
BCS
1
0
1
2
1
Bit 0
1
1
1
1
1
1
0
0
0
0
0
0
VRS6
VRS5
VRS4
1
1
0
2
1
Bit 0
1
1
1
1
1
1
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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