Table 3-9. Ipic Memory Map-Control And Status Registers - Motorola MVME162 User Manual

Operating Instructions
Table 3-9 contains a summary of the IPIC CSR registers. The CSR registers can
be accessed as bytes, words, or longwords; they should not be accessed as
lines. They are shown in the table as bytes.
3
Table 3-9. IPIC Memory Map—Control and Status Registers
IPIC Base Address = $FFFBC000
Register Register
Offset Name
$00 CHIP ID
$01 CHIP REVISION
$02 RESERVED
$03 RESERVED
$04 IP_a MEM BASE UPPER
$05
IP_a MEM BASE LOWER
$06
IP_b MEM BASE UPPER
$07
IP_b MEM BASE LOWER
$08 IP_c MEM BASE UPPER
$09
IP_c MEM BASE LOWER
$0A
IP_d MEM BASE UPPER
$0B
IP_d MEM BASE LOWER
$0C IP_a MEM SIZE
$0D
IP_b MEM SIZE
$0E
IP_c MEM SIZE
$0F
IP_d MEM SIZE
$10
IP_a INT0 CONTROL
$11
IP_a INT1 CONTROL
$12
IP_b INT0 CONTROL
$13 IP_b INT1 CONTROL
$14
IP_c INT0 CONTROL
$15
IP_c INT1 CONTROL
$16
IP_d INT0 CONTROL
$17
IP_d INT1 CONTROL
$18
IP_a GENERAL
CONTROL
$19
IP_a GENERAL
CONTROL
3-18
D7 D6 D5
0 0 1
0 0 0
0 0 0
0 0 0
a_BASE31 a_BASE30 a_BASE29
a_BASE23 a_BASE22 a_BASE21
b_BASE31 b_BASE30 b_BASE29
b_BASE23 b_BASE22 b_BASE21
c_BASE31 c_BASE30 c_BASE29
c_BASE23 c_BASE22 c_BASE21
d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27
d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19
a_SIZE23 a_SIZE21
a_SIZE22
b_SIZE23 b_SIZE22 b_SIZE21
c_SIZE23 c_SIZE22 c_SIZE21
d_SIZE23 d_SIZE22 d_SIZE21
a0_PLTY a0_E/L* a0_INT
a1_PLTY a1_E/L* a1_INT
b0_PLTY b0_E/L* b0_INT
b1_PLTY b1_E/L* b1_INT
c0_PLTY c0_E/L* c0_INT
c1_PLTY c1_E/L* c1_INT
d0_PLTY d0_E/L* d0_INT
d1_PLTY d1_E/L* d1_INT
a_ERR a_RT1
0
b_ERR 0 b_RT1
Register Bit Names
D4 D3 D2
0 0 0
0 0 0
0 0 0
0 0 0
a_BASE28 a_BASE27 a_BASE26
a_BASE20 a_BASE19 a_BASE18
b_BASE26
b_BASE28 b_BASE27
b_BASE20 b_BASE19 b_BASE18
c_BASE28 c_BASE27 c_BASE26
c_BASE20 c_BASE19 c_BASE18
d_BASE26
d_BASE18
a_SIZE18
a_SIZE20 a_SIZE19
b_SIZE20 b_SIZE19 b_SIZE18
c_SIZE20 c_SIZE19 c_SIZE18
d_SIZE20 d_SIZE19 d_SIZE18
a0_IEN a0_ICLR a0_IL2
a1_IEN a1_ICLR a1_IL2
b0_IEN b0_ICLR b0_IL2
b1_IEN b1_ICLR b1_IL2
c0_IEN c0_ICLR c0_IL2
c1_IEN c1_ICLR c1_IL2
d0_IEN d0_ICLR d0_IL2
d1_IEN d1_ICLR d1_IL2
0
a_RT a_WIDTH1 a_WIDTH
b_RT0 b_WIDTH1 b_WIDTH0
D1 D0
1 1
0 0
0 0
0 0
a_BASE25 a_BASE24
a_BASE17 a_BASE16
b_BASE25
b_BASE24
b_BASE17 b_BASE16
c_BASE25 c_BASE24
c_BASE17 c_BASE16
d_BASE25
d_BASE24
d_BASE17 d_BASE16
a_SIZE17 a_SIZE16
b_SIZE17 b_SIZE16
c_SIZE17 c_SIZE16
d_SIZE17 d_SIZE16
a0_IL1 a0_IL0
a1_IL1 a1_IL0
b0_IL1 b0_IL0
b1_IL1 b1_IL0
c0_IL1 c0_IL0
c1_IL1 c1_IL0
d0_IL1 d0_IL0
d1_IL1 d1_IL0
0
a_MEN
0
0 b_MEN
User's Manual