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8.8 SIM Registers
8.8.1 SIM Break Status Register
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
The SIM has three memory mapped registers.
mapping of these registers.
Address
$FE00
$FE01
$FE03
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop or wait mode.
Address:
$FE00
Bit 7
Read:
R
Write:
Reset:
0
R
= Reserved
Note: 1. Writing a logic 0 clears SBSW.
Figure 8-17. SIM Break Status Register (SBSR)
SBSW — SIM Break STOP/WAIT
This status bit is useful in applications requiring a return to stop or wait
mode after exiting from a break interrupt. SBSW can be cleared by
writing a logic 0 to it. Reset clears SBSW.
1 = Stop or wait mode was exited by break interrupt
0 = Stop or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this.
System Integration Module (SIM)
Table 8-4. SIM Registers
Register
SBSR
SRSR
SBFCR
6
5
4
R
R
R
0
0
0
System Integration Module (SIM)
SIM Registers
Table 8-4
shows the
Access Mode
User
User
User
3
2
1
SBSW
R
R
(1)
Note
0
0
0
Technical Data
Bit 0
R
0
127
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