Flag Clearing Sequence - Motorola MC68HC908AB32 Technical Data Manual

Serial Communications Interface
BYTE 1
BYTE 1
Technical Data
272
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
READ SCS1 READ SCS1
SCRF = 1
OR = 0
READ SCDR READ SCDR
BYTE 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
Figure 15-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
Serial Communications Interface Module (SCI)
BYTE 3
READ SCS1
SCRF = 1 SCRF = 1
OR = 0
READ SCDR
BYTE 2 BYTE 3
BYTE 3
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
BYTE 4
OR = 0
BYTE 4
MC68HC908AB32 Rev. 1.0
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MOTOROLA