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NOTE:
NOTE:
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Table 9-1. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
1101
1110
1111
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f
. (See
9.4.2.1 PLL
VRS
9.6.1 PLL Control Register
when the PLLON bit in the PLL control register (PCTL) is set. (See
9.4.2.5 Special Programming
VCO range select bits disables the PLL and clears the BCS bit in the
PCTL. (See
9.4.3 Base Clock Selector Circuit
Programming Exceptions
the bits to $6 to give a default range multiply value of 6.
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
Clock Generator Module (CGM)
VCO Frequency Multiplier (N)
Circuits,
9.4.2.4 Programming the
(PCTL)). VRS[7:4] cannot be written
Exceptions). A value of $0 in the
for more information). Reset initializes
Clock Generator Module (CGM)
CGM Registers
1
1
2
3
13
14
15
PLL, and
and
9.4.2.5 Special
Technical Data
149
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