Motorola MC68HC908AB32 Technical Data Manual
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Motorola MC68HC908AB32 Technical Data Manual

Motorola MC68HC908AB32 Technical Data Manual

Hcmos microcontroller unit
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MC68HC908AB32/D
REV. 1.0
MC68HC908AB32
HCMOS Microcontroller Unit
TECHNICAL DATA

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Summary of Contents for Motorola MC68HC908AB32

  • Page 1 MC68HC908AB32/D REV. 1.0 MC68HC908AB32 HCMOS Microcontroller Unit TECHNICAL DATA...

  • Page 3: Table Of Contents

    Technical Data — MC68HC908AB32 List of Sections Section 1. General Description ....29 Section 2. Memory Map ......41 Section 3.
  • Page 4 Section 24. Mechanical Specifications ... . .387 Section 25. Ordering Information ....389 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 5 Technical Data — MC68HC908AB32 Table of Contents Section 1. General Description Contents ......... . 29 Introduction .
  • Page 6 Introduction ........69 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 7 Features ......... . 90 MC68HC908AB32 Rev.
  • Page 8 SIM Counter during Stop Mode Recovery ... . . 118 8.5.3 SIM Counter and Reset States..... . 118 Technical Data MC68HC908AB32 Rev. 1.0 — Table of Contents...
  • Page 9 External Filter Capacitor Pin (CGMXFC) ....142 9.5.4 PLL Analog Power Pin (V ) ..... . 142 MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 10 Extended Security........168 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 11 11.10.4 TIMA Channel Status and Control Registers ... 188 11.10.5 TIMA Channel Registers ......192 MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 12 12.10.4 TIMB Channel Status and Control Registers ... 214 12.10.5 TIMB Channel Registers ......218 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 13 I/O Signals ........233 14.7.1 ADC Analog Power Pin (V )....234 DDAREF MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...
  • Page 14 Wait Mode ........259 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 15 Interrupts......... 296 MC68HC908AB32 Rev.
  • Page 16 Data Direction Register D (DDRD)....324 17.6.3 Port D Input Pullup Enable Register (PTDPUE)..325 Technical Data MC68HC908AB32 Rev. 1.0 — Table of Contents...
  • Page 17 Keyboard Initialization ......349 19.5.2 Keyboard Status and Control Register....349 MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 18 Features ......... 359 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 19 Introduction ........373 23.3 Absolute Maximum Ratings ......374 MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 20 MC Order Numbers ....... . 389 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 21 Page MC68HC908AB32 Block Diagram ..... . 32 64-Pin QFP Pin Assignment ......33 Power Supply Bypassing .
  • Page 22 11-1 TIMA Block Diagram....... . 172 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 23 12-14 TIMB Channel 0 Register High (TBCH0H) ....218 12-15 TIMB Channel 0 Register Low (TBCH0L)....218 MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 24 15-15 SCI Data Register (SCDR) ......274 15-16 SCI Baud Rate Register (SCBR) ..... . 275 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 25 17-20 Port F I/O Circuit ........331 MC68HC908AB32 Rev.
  • Page 26 23-2 SPI Slave Timing ........382 24-1 64-Pin Plastic Quad Flat Pack (QFP) ....388 Technical Data MC68HC908AB32 Rev. 1.0 —...
  • Page 27 Technical Data — MC68HC908AB32 List of Tables Table Title Page I/O Pins Summary........38 Signal Name Conventions .
  • Page 28 25-1 MC Order Numbers ....... . 389 Technical Data MC68HC908AB32 Rev. 1.0 —...

  • Page 29: Contents

    Technical Data — MC68HC908AB32 Section 1. General Description 1.1 Contents Introduction ........30 Features .

  • Page 30: Section 1. General Description

    Low-power design (fully static with STOP and WAIT modes) • Master reset pin and power-on reset 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data MC68HC908AB32 Rev.

  • Page 31: Mcu Block Diagram

    Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.4 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908AB32. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA General Description...

  • Page 32: Mc68Hc908Ab32 Block Diagram

    PTH1/KBD4 – PTH0/KBD3 ** † Ports are software configurable with pullup device if input port. ‡ Higher current drive port pins * Pin contains integrated pullup device ** Pullup enabled when configured as keyboard interrupt pin Figure 1-1. MC68HC908AB32 Block Diagram...

  • Page 33: Pin Assignments

    General Description Pin Assignments 1.5 Pin Assignments Figure 1-2 shows the pin assignment for the MC68HC908AB32. PTC4 PTH0/KBD3 PTD3 PTD2 PTF0/TACH2 /VREFL PTF1/TACH3 DDAREF PTF2/TBCH2 PTD1 PTF3/TBCH3 PTD0 PTB7/ATD7 PTF4/TBCH0 PTB6/ATD6 PTF7 PTB5/ATD5 PTF5/TBCH1 PTB4/ATD4 PTF6 PTB3/ATD3 PTE0/TxD PTB2/ATD2 PTE1/RxD...

  • Page 34: Pin Functions

    (SPI). See Section 16. Serial Peripheral Interface Module (SPI). must be grounded for proper MCU operation. Technical Data MC68HC908AB32 Rev. 1.0 — General Description MOTOROLA...

  • Page 35: Oscillator Pins (Osc1 And Osc2)

    /VREFL) The A analog ground pin is used only for the ground connections for the analog to digital convertor (ADC) and should be decoupled as per the V digital ground pin. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA General Description...

  • Page 36: Adc Voltage Reference Pin (Vrefh)

    1.6.13 Port C I/O Pins (PTC5–PTC0) PTC5–PTC0 are general-purpose bidirectional I/O port pins. PTC2 is a special function port pin that is shared with the system clock output pin, MCLK. See Section 17. Input/Output (I/O) Ports. Technical Data MC68HC908AB32 Rev. 1.0 — General Description MOTOROLA...

  • Page 37: Port D I/O Pins (Ptd7-Ptd0)

    Section 17. Input/Output (I/O) Ports. 1.6.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3) PTH1–PTH0 are general-purpose bidirectional I/O pins with Keyboard wakeup function. See Section 19. Keyboard Interrupt Module (KBI) Section 17. Input/Output (I/O) Ports. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA General Description...

  • Page 38: I/O Pin Summary

    General purpose I/O PTE0/TxD Dual State Input (Hi-Z) / SCI transmit data PTF7–PTF6 General purpose I/O Dual State Input (Hi-Z) General purpose I/O PTF5/TBCH1 Dual State Input (Hi-Z) / Timer B channel 1 Technical Data MC68HC908AB32 Rev. 1.0 — General Description MOTOROLA...
  • Page 39 PLL loop filter cap External interrupt request Input (pullup) Reset Input (pullup) Details of the clock connections to each of the modules on the MC68HC908AB32 are shown in Table 1-2. A short description of each clock source is also given in Table 1-3.

  • Page 40: Signal Name Conventions

    CGMXCLK or bus clock CGMXCLK Bus clock EEPROM CGMXCLK or bus clock Bus clock Bus clock SPSCK CGMXCLK TIMA Bus clock or PTD6/TACLK TIMB Bus clock or PTD4/TBCLK Bus clock Bus clock Technical Data MC68HC908AB32 Rev. 1.0 — General Description MOTOROLA...

  • Page 41: Section 2. Memory Map

    Technical Data — MC68HC908AB32 Section 2. Memory Map 2.1 Contents Introduction ........41 Unimplemented Memory Locations .

  • Page 42: Reserved Memory Locations

    $FE1F; EEPROM array configuration register, EEACR • $FF7E; FLASH block protect register, FLBPR • $FFFF; COP control register, COPCTL Data registers are shown in Figure 2-2, Table 2-1 is a list of vector locations. Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...

  • Page 43: Section 4. Flash Memory

    SIM Break Status Register (SBSR) $FE01 SIM Reset Status Register (SRSR) $FE02 Reserved $FE03 SIM Break Flag Control Register (SBFCR) $FE04 Reserved ↓ 4 Bytes $FE07 $FE08 FLASH Control Register (FLCR) Figure 2-1. Memory Map MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...
  • Page 44 $FF7F Unimplemented ↓ 65 Bytes $FFBF $FFC0 Reserved FLASH Memory ↓ 16 Bytes Reserved for Compatibility with HC08AB16/24/32 $FFCF $FFD0 FLASH Vectors ↓ 48 Bytes $FFFF Figure 2-1. Memory Map (Continued) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...

  • Page 45: Control, Status, And Data Registers

    PTF4 PTF3 PTF2 PTF1 PTF0 Port F Data Register $0009 Write: (PTF) Reset: Unaffected by reset = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 11) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...
  • Page 46 Unaffected by reset Read: LOOPS ENSCI TXINV WAKE ILTY SCI Control Register 1 $0013 Write: (SCC1) Reset: = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 11) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...
  • Page 47 PLL Control Register $001C Write: (PCTL) Reset: Read: LOCK PLL Bandwidth Control AUTO $001D Register Write: (PBWC) Reset: = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 11) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...
  • Page 48 Timer A Channel 0 Bit 15 Bit 8 $0027 Register High Write: (TACH0H) Reset: Indeterminate after reset = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 11) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...
  • Page 49 Timer A Channel 3 Bit 7 Bit 0 $0031 Register Low Write: (TACH3L) Reset: Indeterminate after reset = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 11) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...
  • Page 50 Analog-to-Digital Clock ADIV2 ADIV1 ADIV0 ADICLK $003A Register Write: (ADCLK) Reset: Read: $003B Reserved Write: Reset: = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 11) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...
  • Page 51 Timer B Channel 0 Status CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0045 and Control Register Write: (TBSC0) Reset: = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 11) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...
  • Page 52 (PMODH) Reset: Read: PIT Counter Modulo Bit 7 Bit 0 $004F Register Low Write: (PMODL) Reset: = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 11) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...
  • Page 53 Read: HVEN MASS ERASE FLASH Control Register $FE08 Write: (FLCR) Reset: Read: $FE09 Reserved Write: Reset: = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 11) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...
  • Page 54 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EE Divider Register Low $FE1B Write: (EEDIVL) Reset: Contents of EEDIVLNVR ($FE11) = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 11) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...
  • Page 55 COP Control Register $FFFF Write: Writing clears COP counter (any value) (COPCTL) Reset: Unaffected by reset = Unimplemented = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 11) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Memory Map...

  • Page 56: Vector Addresses

    PLL Vector (High) $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High) Highest $FFFF Reset Vector (Low) Technical Data MC68HC908AB32 Rev. 1.0 — Memory Map MOTOROLA...

  • Page 57: Contents

    Technical Data — MC68HC908AB32 Section 3. Random-Access Memory (RAM) 3.1 Contents Introduction ........57 Functional Description .
  • Page 58 The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data MC68HC908AB32 Rev. 1.0 — Random-Access Memory (RAM) MOTOROLA...

  • Page 59: Contents

    Technical Data — MC68HC908AB32 Section 4. FLASH Memory 4.1 Contents Introduction ........59 Functional Description .

  • Page 60: Flash Control Register

    1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

  • Page 61: Flash Page Erase Operation

    4. Wait for a time, t (min. 10µs) 5. Set the HVEN bit. 6. Wait for a time, t (min. 1ms) Erase 7. Clear the ERASE bit. 8. Wait for a time, t (min. 5µs) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA FLASH Memory...

  • Page 62: Flash Mass Erase Operation

    Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Technical Data MC68HC908AB32 Rev. 1.0 — FLASH Memory MOTOROLA...

  • Page 63: Flash Program/Read Operation

    * The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t max. PROG This program sequence is repeated throughout the memory until all data is programmed. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA FLASH Memory...

  • Page 64: Flash Block Protection

    The FLBPR itself can be erased or programmed only with an external voltage, V , present on the IRQ pin. This voltage also allows entry from reset into the monitor mode. Technical Data MC68HC908AB32 Rev. 1.0 — FLASH Memory MOTOROLA...

  • Page 65: Flash Programming Flowchart

    PROG Clear HVEN bit This row program algorithm assumes the row/s to be programmed are initially erased. Wait for a time, t End of programming Figure 4-2. FLASH Programming Flowchart MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA FLASH Memory...

  • Page 66: Flash Block Protect Register

    (128 bytes page boundaries) within the FLASH memory. 16-bit memory address Start address of FLASH block protect 0 0 0 0 0 0 0 FLBPR value Figure 4-4. FLASH Block Protect Start Address Technical Data MC68HC908AB32 Rev. 1.0 — FLASH Memory MOTOROLA...

  • Page 67: Wait Mode

    NOTE: Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum. MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 68 FLASH Memory Technical Data MC68HC908AB32 Rev. 1.0 — FLASH Memory MOTOROLA...

  • Page 69: Introduction

    Technical Data — MC68HC908AB32 Section 5. EEPROM 5.1 Contents Introduction ........69 Features .

  • Page 70: Features

    EEBP2 EEBP1 EEBP0 EEPROM Array $FE1F Configuration Register Write: (EEACR) Reset: Contents of EENVR ($FE1C) * Non-volatile EEPROM register; write by programming. = Unimplemented = Reserved Figure 5-1. EEPROM I/O Register Summary Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 71: Functional Description

    For EENVR, the corresponding volatile register is the EEPROM array configuration register (EEACR). For the EEDIVNVR (two 8-bit registers: EEDIVHNVR and EEDIVLNVR), the corresponding volatile register is the EEPROM timebase divider register (EEDIV: EEDIVH and EEDIVL) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 72: Eeprom Timebase Requirements

    The 512 bytes of EEPROM is divided into four 128-byte blocks. Each of these blocks can be protected from erase/program operations by setting the EEBPx bit in the EENVR. Table 5-1 shows the address ranges for the blocks. Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 73: Eeprom Programming And Erasing

    That is, if the same byte is programmed eight times (with any value), that byte must be erased before it can be successfully programmed again. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 74: Eeprom Programming

    EEPROM address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM locations, otherwise the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 75: Eeprom Erasing

    6. Wait for a time, t , for the erasing voltage to fall. EEFPV Go to step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer. 8. Clear EELAT bits. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA EEPROM...

  • Page 76: Low Power Modes

    5.10.1 Wait Mode The WAIT instruction does not affect the EEPROM. It is possible to start the program or erase sequence on the EEPROM and put the MCU in wait mode. Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 77: Stop Mode

    Address: $FE1D Bit 7 Bit 0 Read: EEDUM EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM Write: Reset: Figure 5-2. EEPROM Control Register (EECR) EEDUM — Dummy Bit This read/write bit has no function. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA EEPROM...

  • Page 78: Eeprom Program/Erase Mode Select

    (See note D for 5.9.1 EEPROM Programming 5.9.2 EEPROM Erasing.) 0 = Automatic clear of EEPGM is disabled 1 = Automatic clear of EEPGM is enabled Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 79: Eeprom Array Configuration Register

    EEPRTCT — EEPROM Protection Bit The EEPRTCT bit is used to enable the security feature in the EEPROM (see 5.7 EEPROM Security Options). 1 = EEPROM security disabled 0 = EEPROM security enabled MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA EEPROM...

  • Page 80: Eeprom Non-Volatile Register

    The 16-bit EEPROM timebase divider register consists of two 8-bit registers: EEDIVH and EEDIVL. The 11-bit value in this register is used to configure the timebase divider circuit to obtain the 35µs timebase for EEPROM control. Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 81: Eeprom Divider Register High (Eedivh)

    35µs from the selected reference clock source (CGMXCLK or bus clock, see 6.5 Configuration Register for the EEPROM related internal timer and circuits. EEDIV[10:0] bits are readable at any time. They are writable when EELAT=0 and EEDIVSECD=1. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA EEPROM...

  • Page 82: Eeprom Timebase Divider Non-Volatile Register

    Figure 5-7. EEPROM Divider Non-volatile Register High(EEDIVHNVR) Address: $FE11 Bit 7 Bit 0 Read: EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 Write: Reset: Unaffected by reset; $FF when blank Figure 5-8. EEPROM Divider Non-volatile Register Low (EEDIVLNVR) Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...
  • Page 83 Once this security feature is armed, erase and program operations are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the EEDIVH and EEDIVL registers are also disabled. Therefore, care should be taken before programming a value into the EEDIVHNVR. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...
  • Page 84 EEPROM Technical Data MC68HC908AB32 Rev. 1.0 — EEPROM MOTOROLA...

  • Page 85: Section 6. Configuration Register (Config)

    Technical Data — MC68HC908AB32 Section 6. Configuration Register (CONFIG) 6.1 Contents Introduction ........85 Functional description.

  • Page 86: Configuration Register 1 (Config1)

    LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. (See Section 21. Low-Voltage Inhibit (LVI).) 1 = LVI module resets disabled 0 = LVI module resets enabled Technical Data MC68HC908AB32 Rev. 1.0 — Configuration Register (CONFIG) MOTOROLA...
  • Page 87 ROM code request submitted. The enable/disable logic is not necessarily identical in all parts of the AB, AS, and AZ families. If in doubt, check with your local field applications representative. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 88: Configuration Register 2 (Config2)

    ROM code request submitted. The enable/disable logic is not necessarily identical in all parts of the AB, AS, and AZ families. If in doubt, check with your local field applications representative. Technical Data MC68HC908AB32 Rev. 1.0 — Configuration Register (CONFIG) MOTOROLA...

  • Page 89: Introduction

    7.2 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

  • Page 90: Cpu Registers

    64K-bytes • Low-power stop and wait modes 7.4 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...

  • Page 91: Accumulator

    The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Bit 0 Read: Write: Reset: Unaffected by reset Figure 7-2. Accumulator (A) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)

  • Page 92: Index Register

    The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU)

  • Page 93: Program Counter

    Figure 7-5. Program Counter (PC) 7.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 94: Condition Code Register (Ccr)

    H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...
  • Page 95 Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)

  • Page 96: Arithmetic/Logic Unit (Alu)

    The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.

  • Page 97: Stop Mode

    A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. 7.8 Instruction Set Summary 7.9 Opcode Map Table 7-2. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)

  • Page 98: Instruction Set Summary

    DIR (b2) DIR (b3) Mn ← 0 BCLR n , opr Clear Bit n in M – – – – – – DIR (b4) DIR (b5) DIR (b6) DIR (b7) Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...
  • Page 99 BPL rel Branch if Plus – – – – – – REL PC ← (PC) + 2 + rel BRA rel Branch Always – – – – – – REL MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)
  • Page 100 H ← $00 CLRH Clear 0 – – 0 1 – M ← $00 CLR opr ,X M ← $00 CLR ,X M ← $00 CLR opr ,SP 9E6F Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...
  • Page 101 DEC opr ,X M ← (M) – 1 DEC ,X M ← (M) – 1 DEC opr ,SP 9E6A A ← (H:A)/(X) Divide – – – – H ← Remainder MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)
  • Page 102 LDX opr ,SP 9EEE LDX opr ,SP 9EDE ee ff LSL opr LSLA LSLX Logical Shift Left – – LSL opr ,X (Same as ASL) LSL ,X LSL opr ,SP 9E68 Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...
  • Page 103 Pull X from Stack – – – – – – INH ROL opr ROLA ROLX Rotate Left through Carry – – ROL opr ,X ROL ,X ROL opr ,SP 9E69 MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)
  • Page 104 STX opr ,X ee ff M ← (X) STX opr ,X Store X in M 0 – – – STX ,X STX opr ,SP 9EEF STX opr ,SP 9EDF ee ff Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...
  • Page 105 A ← (X) Transfer X to A – – – – – – INH (SP) ← (H:X) – 1 Transfer H:X to SP – – – – – – INH MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Central Processor Unit (CPU)
  • Page 106 Indexed, 8-bit offset addressing mode Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Concatenated with Memory location Set or cleared Negative bit — Not affected Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...

  • Page 107: Opcode Map

    Table 7-2. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory BRSET0 BSET0 NEGA NEGX BRCLR0 BCLR0 CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ 3 IX1+ BRSET1 BSET1 BRCLR1 BCLR1 COMA COMX BRSET2 BSET2 LSRA LSRX BRCLR2 BCLR2 STHX LDHX LDHX CPHX CPHX BRSET3 BSET3...
  • Page 108 Central Processor Unit (CPU) Technical Data MC68HC908AB32 Rev. 1.0 — Central Processor Unit (CPU) MOTOROLA...

  • Page 109: Section 8. System Integration Module (Sim)

    Technical Data — MC68HC908AB32 Section 8. System Integration Module (SIM) 8.1 Contents Introduction ........110 SIM Bus Clock Control and Generation .

  • Page 110: Introduction

    – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 8-1 shows the internal signal names used in this section. Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 111: Signal Naming Conventions

    (Bus clock = CGMOUT divided by two) Internal address bus Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal Read/write signal MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA System Integration Module (SIM)

  • Page 112: Sim Bus Clock Control And Generation

    SIM COUNTER CLOCK CGMOUT ÷ ÷ BUS CLOCK SELECT GENERATORS CIRCUIT CGMVCLK When S = 1, CGMOUT = B PTC3 MONITOR MODE USER MODE Figure 8-3. CGM Clock Signals Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 113: Bus Timing

    The MCU has the following reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA System Integration Module (SIM)

  • Page 114: External Pin Reset

    POR resets, the SIM cycles through 4096 CGMXCLK cycles, during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST as shown in Figure 8-5. Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 115: Power-On Reset

    The internal reset signal is asserted • The SIM enables CGMOUT • Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow the oscillator to stabilize MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA System Integration Module (SIM)

  • Page 116: Computer Operating Properly (Cop) Reset

    RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V on the RST pin disables the COP module. Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 117: Illegal Opcode Reset

    (COP) module. The SIM counter overflow supplies the clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 118: Sim Counter During Power-On Reset

    Normal, sequential program execution can be changed in three different ways: • Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 119: Interrupts

    Once an interrupt is latched by the SIM, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the I-bit is cleared). (See Figure 8-10.) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA System Integration Module (SIM)

  • Page 120: Hardware Interrupts

    If interrupts are not masked (I-bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 121: Swi Instruction

    (I-bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 122: Vector Addresses

    $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High) Highest $FFFF Reset Vector (Low) Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 123: Reset

    — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 124: Low-Power Modes

    NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 8-12. Wait Mode Entry Timing Figure 8-13 Figure 8-14 show the timing for wait recovery. Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 125: Stop Mode

    NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA System Integration Module (SIM)

  • Page 126: Stop Mode Entry Timing

    STOP RECOVERY PERIOD CGMXCLK INT/BREAK STOP +1 STOP + 2 STOP + 2 SP – 1 SP – 2 SP – 3 Figure 8-16. Stop Mode Recovery from Interrupt or Break Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 127: Sim Registers

    0 = Stop or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 128: Sim Reset Status Register

    Write: Reset: = Unimplemented Figure 8-18. SIM Reset Status Register (SRSR) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 129: Sim Break Flag Control Register

    MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 130 System Integration Module (SIM) Technical Data MC68HC908AB32 Rev. 1.0 — System Integration Module (SIM) MOTOROLA...

  • Page 131: Section 9. Clock Generator Module (Cgm)

    Technical Data — MC68HC908AB32 Section 9. Clock Generator Module (CGM) 9.1 Contents Introduction ........132 Features .

  • Page 132: Introduction

    Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation • Automatic bandwidth control mode for low-jitter operation • Automatic frequency lock detector • CPU interrupt on entry or exit from locked condition Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 133: Functional Description

    PHASE LOOP CONTROLLED DETECTOR FILTER OSCILLATOR PLL ANALOG CGMINT LOCK BANDWIDTH INTERRUPT DETECTOR CONTROL CONTROL LOCK AUTO PLLIE PLLF MUL[7:4] CGMVDV CGMVCLK FREQUENCY DIVIDER Figure 9-1. CGM Block Diagram MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Clock Generator Module (CGM)

  • Page 134: Crystal Oscillator Circuit

    An externally generated clock can also feed the OSC1 pin of the crystal oscillator circuit. For this configuration, the external clock should be connected to the OSC1 pin and the OSC2 pin allowed to float. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM)

  • Page 135: Phase-Locked Loop (Pll) Circuit

    The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 136: Acquisition And Tracking Modes

    ACQ bit is set. 9.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...
  • Page 137 The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below f BUSMAX MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 138: Programming The Pll

    × VCLKDES BUSDES 3. Choose a practical PLL reference frequency, f RCLK 4. Select a VCO frequency multiplier, N.   VCLKDES round --------------------- -   RCLK Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 139: Special Programming Exceptions

    9.4.2.4 Programming the PLL does not account for two possible exceptions — a value of zero for N or L is meaningless when used in the equations given. To account for these exceptions: MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 140: Base Clock Selector Circuit

    Figure 9-3. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 141: Cgm External Connections

    PLL performance). SIMOSCEN CGMXCLK OSC1 OSC2 CGMXFC can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. Figure 9-3. CGM External Connections MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Clock Generator Module (CGM)

  • Page 142: I/O Signals

    9.5.5 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 143: Crystal Output Frequency Signal (Cgmxclk)

    PLL bandwidth control register (PBWC). (See 9.6.2 PLL Bandwidth Control Register (PBWC)) • PLL programming register (PPG). (See 9.6.3 PLL Programming Register (PPG)) Figure 9-4 is a summary of the CGM registers. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Clock Generator Module (CGM)

  • Page 144: Pll Control Register (Pctl)

    The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. Address: $001C Bit 7 Bit 0 Read: PLLF PLLIE PLLON Write: Reset: = Unimplemented Figure 9-5. PLL Control Register (PCTL) Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...
  • Page 145 BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 146: Pll Bandwidth Control Register (Pbwc)

    In manual operation, forces the PLL into acquisition or tracking mode. Address: $001D Bit 7 Bit 0 Read: LOCK AUTO Write: Reset: = Unimplemented Figure 9-7. PLL Bandwidth Control Register (PBWC) Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...
  • Page 147 1. Write a 1 to XLD. 2. Wait 4 × N cycles. (N is the VCO frequency multiplier.) 3. Read XLD. 1 = Crystal reference is not active 0 = Crystal reference is active MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 148: Pll Programming Register (Ppg)

    PLL). A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 149: Vco Frequency Multiplier (N) Selection

    VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 150: Interrupts

    PLL without turning it off. Applications that require the PLL to wake the MCU from WAIT mode also can deselect the PLL output without turning off the PLL. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM)

  • Page 151: Stop Mode

    9.10 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 152: Acquisition/Lock Time Definitions

    – f ORIG bandwidth control mode (see 9.4.2.3 Manual and Automatic PLL Bandwidth Modes), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC). Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 153: Parametric Influences On Reaction Time

    If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. See 9.10.3 Choosing a Filter Capacitor. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 154: Choosing A Filter Capacitor

    PLL may become unstable. Also, always choose a capacitor with a tight tolerance (±20% or better) and low dissipation. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM)

  • Page 155: Reaction Time Calculation

    , is required to ascertain whether the PLL is within the tracking mode entry tolerance ∆ , before exiting acquisition mode. Also, a certain number of clock cycles, n , is required to ascertain MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...
  • Page 156 PLL clock (see 9.4.3 Base Clock Selector LOCK Circuit), because the factors described in 9.10.2 Parametric Influences On Reaction Time may slow the lock time considerably. Technical Data MC68HC908AB32 Rev. 1.0 — Clock Generator Module (CGM) MOTOROLA...

  • Page 157: Contents

    Technical Data — MC68HC908AB32 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction ........157 10.3...

  • Page 158: Section 10. Monitor Rom (Mon)

    PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

  • Page 159: Monitor Mode Circuit

    Monitor ROM (MON) Functional Description MC68HC908AB32 10 kΩ 0.1 µF 10 Ω CGMXFC 0.1 µF MC145407 10 µF 10 µF OSC1 20 pF 10 MΩ 10 µF 10 µF 4.9152 MHz OSC2 20 pF DB-25 0.1 µF MC74HC125 10 kΩ...

  • Page 160: Entering Monitor Mode

    CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. Technical Data MC68HC908AB32 Rev. 1.0 — Monitor ROM (MON) MOTOROLA...

  • Page 161: Data Format

    BIT 5 BIT 6 BIT 7 STOP START BREAK BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Figure 10-3. Sample Monitor Waveforms MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Monitor ROM (MON)

  • Page 162: Echoing

    When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO Figure 10-5. Break Transaction Technical Data MC68HC908AB32 Rev. 1.0 — Monitor ROM (MON) MOTOROLA...

  • Page 163: Commands

    Specifies 2-byte address in high byte:low byte order Data Returns contents of specified address Returned Opcode Command Sequence SENT TO MONITOR ADDRESS ADDRESS ADDRESS ADDRESS READ READ DATA HIGH HIGH ECHO RETURN MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Monitor ROM (MON)

  • Page 164: Write (Write Memory) Command

    Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returns contents of next two addresses Returned Opcode Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA ECHO RETURN Technical Data MC68HC908AB32 Rev. 1.0 — Monitor ROM (MON) MOTOROLA...

  • Page 165: Iwrite (Indexed Write) Command

    Table 10-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returns stack pointer in high byte:low byte order Returned Opcode Command Sequence SENT TO MONITOR READSP READSP HIGH ECHO RETURN MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Monitor ROM (MON)

  • Page 166: Baud Rate

    (CGM).) Table 10-9. Monitor Baud Rate Selection VCO Frequency Multiplier (N) Monitor Baud Rate 4.9152 MHz 4800 9600 14,400 19,200 24,000 28,800 4.194 MHz 4096 8192 12,288 16,384 20,480 24,576 Technical Data MC68HC908AB32 Rev. 1.0 — Monitor ROM (MON) MOTOROLA...

  • Page 167: Security

    NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. Figure 10-6. Monitor Mode Entry Timing MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Monitor ROM (MON)

  • Page 168: Extended Security

    FLASH locations $FFC0–$FFC7. The keyword is eight bytes long with a 7-byte ASCII string and 1-byte $00 delimiter. The keyword for the MC68HC908AB32 MCU is "PSWDOPT" + $00. Entry to monitor mode with extended security command keyword...

  • Page 169: Contents

    Technical Data — MC68HC908AB32 Section 11. Timer Interface Module A (TIMA) 11.1 Contents 11.2 Introduction ........170 11.3...

  • Page 170: Section 11. Timer Interface Module A (Tima)

    – External TIMA clock input (4MHz maximum frequency) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIMA counter stop and reset bits • Modular architecture expandable to eight channels Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 171: Pin Name Conventions

    The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 172: Tima Block Diagram

    LOGIC MS2A CH2IE MS2B TOV3 ELS3B ELS3A PTF1 CHANNEL 3 CH3MAX PTF1/TACH3 LOGIC 16-BIT COMPARATOR TACH3H:TACH3L CH3F INTERRUPT 16-BIT LATCH LOGIC MS3A CH3IE Figure 11-1. TIMA Block Diagram Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 173: Tima I/O Register Summary

    Timer A Channel 1 Bit 15 Bit 8 $002A Register High Write: (TACH1H) Reset: Indeterminate after reset = Unimplemented Figure 11-2. TIMA I/O Register Summary (Sheet 1 of 2) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module A (TIMA)

  • Page 174: Input Capture

    TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH:TACHxL. The polarity of the active edge is programmable. Input captures can generate TIMA CPU interrupt requests. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 175: Output Compare

    Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 176: Buffered Output Compare

    In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 177: Pulse Width Modulation (Pwm)

    The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers produces a duty cycle of 128/256 or 50%. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 178: Unbuffered Pwm Signal Generation

    Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA)

  • Page 179: Buffered Pwm Signal Generation

    NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 180: Pwm Initialization

    PWM output. TIMA channel 0 status and control register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA)

  • Page 181: Interrupts

    CHxIE= 1. CHxF and CHxIE are in the TIMA channel x status and control register. 11.7 Low-Power Modes The WAIT and STOP instructions puts the MCU in low-power- consumption standby modes. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 182: Wait Mode

    BCFE is at logic zero. After the break, doing the second step clears the status bit. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA)

  • Page 183: I/O Signals

    11.9.2 TIMA Channel I/O Pins Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF0/TACH2 and PTE3/TACH1 can be configured as buffered output compare or buffered PWM pins. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 184: I/O Registers

    • Prescales the TIMA counter clock Address: $0020 Bit 7 Bit 0 Read: TOIE TSTOP Write: TRST Reset: = Unimplemented Figure 11-4. TIMA Status and Control Register (TASC) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...
  • Page 185 1 = Prescaler and TIMA counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module A (TIMA)

  • Page 186: Tima Counter Registers

    Otherwise, TACNTL retains the value latched during the break. Address: $0022 Bit 7 Bit 0 Read: Bit 15 Bit 8 Write: Reset: = Unimplemented Figure 11-5. TIMA Counter Register High (TACNTH) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 187: Tima Counter Modulo Registers

    Read: Bit 7 Bit 0 Write: Reset: Figure 11-8. TIMA Counter Modulo Register Low (TAMODL) NOTE: Reset the TIMA counter before writing to the TIMA counter modulo registers. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module A (TIMA)

  • Page 188: Tima Channel Status And Control Registers

    Figure 11-9. TIMA Channel 0 Status and Control Register (TASC0) Address: $0029 Bit 7 Bit 0 Read: CH1F CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write: Reset: Figure 11-10. TIMA Channel 1 Status and Control Register (TASC1) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 189: Tima Channel 2 Status And Control Register (Tasc2)

    CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...
  • Page 190 I/O, and pin TACHx is available as a general-purpose I/O pin. Table 11-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 191: Mode, Edge, And Level Selection

    Figure 11-13 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 192: Tima Channel Registers

    Figure 11-14. TIMA Channel 0 Register High (TACH0H) Address: $0028 Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 11-15. TIMA Channel 0 Register Low (TACH0L) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 193: Tima Channel 1 Register High (Tach1H)

    Figure 11-18. TIMA Channel 2 Register High (TACH2H) Address: $002E Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 11-19. TIMA Channel 2 Register Low (TACH2L) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module A (TIMA)

  • Page 194: Tima Channel 3 Register High (Tach3H)

    Figure 11-20. TIMA Channel 3 Register High (TACH3H) Address: $0031 Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 11-21. TIMA Channel 3 Register Low (TACH3L) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module A (TIMA) MOTOROLA...

  • Page 195: Section 12. Timer Interface Module B (Timb)

    Technical Data — MC68HC908AB32 Section 12. Timer Interface Module B (TIMB) 12.1 Contents 12.2 Introduction ........196 12.3...

  • Page 196: Introduction

    – External TIMB clock input (4MHz maximum frequency) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIMB counter stop and reset bits • Modular architecture expandable to eight channels Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 197: Pin Name Conventions

    The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin, PTD4/TBCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 198: Timb Block Diagram

    LOGIC MS2A CH2IE MS2B TOV3 ELS3B ELS3A PTF3 CHANNEL 3 CH3MAX PTF3/TBCH3 LOGIC 16-BIT COMPARATOR TBCH3H:TBCH3L CH3F INTERRUPT 16-BIT LATCH LOGIC MS3A CH3IE Figure 12-1. TIMB Block Diagram Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 199: Timb I/O Register Summary

    Timer B Channel 1 Bit 15 Bit 8 $0049 Register High Write: (TBCH1H) Reset: Indeterminate after reset = Unimplemented Figure 12-2. TIMB I/O Register Summary (Sheet 1 of 2) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module B (TIMB)

  • Page 200: Input Capture

    TIMB latches the contents of the TIMB counter into the TIMB channel registers, TBCHxH:TBCHxL. The polarity of the active edge is programmable. Input captures can generate TIMB CPU interrupt requests. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 201: Output Compare

    Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 202: Buffered Output Compare

    In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 203: Pulse Width Modulation (Pwm)

    The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers produces a duty cycle of 128/256 or 50%. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 204: Unbuffered Pwm Signal Generation

    Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB)

  • Page 205: Buffered Pwm Signal Generation

    NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 206: Pwm Initialization

    PWM output. TIMB channel 0 status and control register (TBSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB)

  • Page 207: Interrupts

    CHxIE= 1. CHxF and CHxIE are in the TIMB channel x status and control register. 12.7 Low-Power Modes The WAIT and STOP instructions puts the MCU in low-power- consumption standby modes. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 208: Wait Mode

    BCFE is at logic zero. After the break, doing the second step clears the status bit. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB)

  • Page 209: I/O Signals

    12.9.2 TIMB Channel I/O Pins Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF2/TBCH2 and PTF5/TBCH1 can be configured as buffered output compare or buffered PWM pins. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 210: I/O Registers

    • Prescales the TIMB counter clock Address: $0040 Bit 7 Bit 0 Read: TOIE TSTOP Write: TRST Reset: = Unimplemented Figure 12-4. TIMB Status and Control Register (TBSC) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...
  • Page 211 1 = Prescaler and TIMB counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB counter at a value of $0000. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module B (TIMB)

  • Page 212: Timb Counter Registers

    Otherwise, TBCNTL retains the value latched during the break. Address: $0041 Bit 7 Bit 0 Read: Bit 15 Bit 8 Write: Reset: = Unimplemented Figure 12-5. TIMB Counter Register High (TBCNTH) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 213: Timb Counter Modulo Registers

    Read: Bit 7 Bit 0 Write: Reset: Figure 12-8. TIMB Counter Modulo Register Low (TBMODL) NOTE: Reset the TIMB counter before writing to the TIMB counter modulo registers. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module B (TIMB)

  • Page 214: Timb Channel Status And Control Registers

    Figure 12-9. TIMB Channel 0 Status and Control Register (TBSC0) Address: $0048 Bit 7 Bit 0 Read: CH1F CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write: Reset: Figure 12-10. TIMB Channel 1 Status and Control Register (TBSC1) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 215: Timb Channel 2 Status And Control Register (Tbsc2)

    CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIMB CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...
  • Page 216 I/O, and pin TBCHx is available as a general-purpose I/O pin. Table 12-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 217: Mode, Edge, And Level Selection

    Figure 12-13 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 218: Timb Channel Registers

    Figure 12-14. TIMB Channel 0 Register High (TBCH0H) Address: $0047 Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 12-15. TIMB Channel 0 Register Low (TBCH0L) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 219: Timb Channel 1 Register High (Tbch1H)

    Figure 12-18. TIMB Channel 2 Register High (TBCH2H) Address: $0034 Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 12-19. TIMB Channel 2 Register Low (TBCH2L) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Timer Interface Module B (TIMB)

  • Page 220: Timb Channel 3 Register High (Tbch3H)

    Figure 12-20. TIMB Channel 3 Register High (TBCH3H) Address: $0037 Bit 7 Bit 0 Read: Bit 7 Bit 0 Write: Reset: Indeterminate after reset Figure 12-21. TIMB Channel 3 Register Low (TBCH3L) Technical Data MC68HC908AB32 Rev. 1.0 — Timer Interface Module B (TIMB) MOTOROLA...

  • Page 221: Section 13. Programmable Interrupt Timer (Pit)

    Technical Data — MC68HC908AB32 Section 13. Programmable Interrupt Timer (PIT) 13.1 Contents 13.2 Introduction ........221 13.3...

  • Page 222: Features

    PRESCALER SELECT INTERNAL PRESCALER BUS CLOCK PSTOP PPS2 PPS1 PPS0 PRST 16-BIT COUNTER INTERRUPT LOGIC POIE 16-BIT COMPARATOR PMODH:PMODL Figure 13-1. PIT Block Diagram Technical Data MC68HC908AB32 Rev. 1.0 — Programmable Interrupt Timer (PIT) MOTOROLA...

  • Page 223: Pit Counter Prescaler

    (POF) is set when the PIT counter value rolls over to $0000 after matching the value in the PIT counter modulo registers. The PIT interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests. POF and POIE are in the PIT status and control register. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 224: Low-Power Modes

    To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status Technical Data MC68HC908AB32 Rev. 1.0 — Programmable Interrupt Timer (PIT)

  • Page 225: I/O Registers

    Prescales the PIT counter clock Address: $004B Bit 7 Bit 0 Read: POIE PSTOP PPS2 PPS1 PPS0 Write: PRST Reset: = Unimplemented Figure 13-3. PIT Status and Control Register (PSC) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Programmable Interrupt Timer (PIT)
  • Page 226 Reset clears the PRST bit. 1 = Prescaler and PIT counter cleared 0 = No effect NOTE: Setting the PSTOP and PRST bits simultaneously stops the PIT counter at a value of $0000. Technical Data MC68HC908AB32 Rev. 1.0 — Programmable Interrupt Timer (PIT) MOTOROLA...

  • Page 227: Pit Counter Registers

    Address: $004C Bit 7 Bit 0 Read: Bit 15 Bit 8 Write: Reset: = Unimplemented Figure 13-4. PIT Counter Register High (PCNTH) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Programmable Interrupt Timer (PIT)

  • Page 228: Pit Counter Modulo Registers

    Bit 0 Read: Bit 7 Bit 0 Write: Reset: Figure 13-7. PIT Counter Modulo Register Low (PMODL) NOTE: Reset the PIT counter before writing to the PIT counter modulo registers. Technical Data MC68HC908AB32 Rev. 1.0 — Programmable Interrupt Timer (PIT) MOTOROLA...

  • Page 229: Section 14. Analog-To-Digital Converter (Adc)

    Technical Data — MC68HC908AB32 Section 14. Analog-to-Digital Converter (ADC) 14.1 Contents 14.2 Introduction ........230 14.3...

  • Page 230: Introduction

    Write: (ADSCR) Reset: Read: $0039 ADC Data Register Write: (ADR) Reset: Read: $003A ADIV2 ADIV1 ADIV0 ADICLK ADC Clock Register Write: (ADCLK) Reset: = Unimplemented Figure 14-1. ADC Register Summary Technical Data MC68HC908AB32 Rev. 1.0 — Analog-to-Digital Converter (ADC) MOTOROLA...

  • Page 231: Functional Description

    ADC DATA REGISTER ADC I/P CHANNELS VOLTAGE IN CONVERSION ADCH[4:0] COMPLETE ADIN CHANNEL INTERRUPT SELECT LOGIC ADC CLOCK AIEN COCO CGMXCLK CLOCK GENERATOR BUS CLOCK ADIV[2:0] ADICLK Figure 14-2. ADC Block Diagram MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Analog-to-Digital Converter (ADC)

  • Page 232: Adc Port I/O Pins

    ADC data register. In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs between writes to the ADSCR. Technical Data MC68HC908AB32 Rev. 1.0 — Analog-to-Digital Converter (ADC)

  • Page 233: Accuracy And Precision

    MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. 14.7 I/O Signals The ADC module has eight pins shared with port B, PTB7/ATD7–PTB0/ATD0. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Analog-to-Digital Converter (ADC)

  • Page 234: Adc Analog Power Pin

    ADC module. 14.8 I/O Registers These I/O registers control and monitor ADC operation: • ADC status and control register (ADSCR) • ADC data register (ADR) • ADC clock register (ADCLK) Technical Data MC68HC908AB32 Rev. 1.0 — Analog-to-Digital Converter (ADC) MOTOROLA...

  • Page 235: Adc Status And Control Register (Adscr)

    ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 236: Mux Channel Select

    PTB5/ATD5 PTB6/ATD6 PTB7/ATD7 ↓ ↓ ↓ ↓ ↓ Reserved REFH REFL ADC power off NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown or reserved. Technical Data MC68HC908AB32 Rev. 1.0 — Analog-to-Digital Converter (ADC) MOTOROLA...

  • Page 237: Adc Data Register (Adr)

    ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 14-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Analog-to-Digital Converter (ADC)

  • Page 238: Adc Clock Divide Ratio

    As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. 1 = Internal bus clock 0 = External clock (CGMXCLK) ADC input clock frequency ----------------------------------------------------------------------- 1MHz ADIV[2:0] Technical Data MC68HC908AB32 Rev. 1.0 — Analog-to-Digital Converter (ADC) MOTOROLA...

  • Page 239: Contents

    Technical Data — MC68HC908AB32 Section 15. Serial Communications Interface Module (SCI) 15.1 Contents 15.2 Introduction ........240 15.3...

  • Page 240: Introduction

    32 programmable baud rates • Programmable 8-bit or 9-bit character length • Separately enabled transmitter and receiver • Separate receiver and transmitter CPU interrupt requests • Programmable transmitter output polarity Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...
  • Page 241 – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 242: Pin Name Conventions

    SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI)

  • Page 243: Sci Module Block Diagram

    RECEIVE FLAG TRANSMIT CONTROL CONTROL CONTROL CONTROL ENSCI WAKE ILTY PRE- BAUD ÷ 4 CGMXCLK SCALER DIVIDER DATA SELECTION ÷ 16 CONTROL Figure 15-1. SCI Module Block Diagram MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 244: Sci I/O Register Summary

    Read: SCP1 SCP0 SCR2 SCR1 SCR0 SCI Baud Rate Register $0019 Write: (SCBR) Reset: = Unimplemented R = Reserved U = Unaffected Figure 15-2. SCI I/O Register Summary Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 245: Data Format

    BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP Figure 15-3. SCI Data Formats 15.5.2 Transmitter Figure 15-4 shows the structure of the SCI transmitter. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 246: Sci Transmitter

    TRANSMIT SCP0 SHIFT REGISTER SCR1 PTE0/TxD SCR2 SCR0 TXINV PARITY GENERATION TRANSMITTER CONTROL LOGIC SCTIE SCTE SCTE SCTE LOOPS SCTIE SCTIE ENSCI TCIE TCIE Figure 15-4. SCI Transmitter Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 247: Character Length

    PTE0/TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 248: Break Characters

    Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI)

  • Page 249: Inversion Of Transmitted Output

    SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 250: Receiver

    SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 251: Sci Receiver Block Diagram

    WAKEUP IDLE LOGIC ILTY PARITY CHECKING IDLE ILIE ILIE SCRF SCRIE SCRIE SCRF SCRIE ORIE ORIE NEIE NEIE FEIE FEIE PEIE PEIE Figure 15-5. SCI Receiver Block Diagram MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 252: Data Sampling

    RT clock begins to count to 16. START BIT PTE1/RxD START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING CLOCK RT CLOCK STATE RT CLOCK RESET Figure 15-6. Receiver Data Sampling Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 253: Start Bit Verification

    RT8, RT9, and RT10. Table 15-3 summarizes the results of the data bit samples. Table 15-3. Data Bit Recovery RT8, RT9, and RT10 Data Bit Noise Flag Samples Determination MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 254: Framing Errors

    Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI)

  • Page 255: Slow Data

    × 4.54% ------------------------- - For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 256: Fast Data

    The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 160 – × ˙ 3.90% ------------------------- - Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 257: Receiver Wakeup

    PTE1/RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 258: Receiver Interrupts

    The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI)

  • Page 259: Low-Power Modes

    Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. Refer to 8.7 Low-Power Modes for information on exiting stop mode. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 260: Sci During Break Module Interrupts

    PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI)

  • Page 261: I/O Registers

    Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 262: Sci Control Register 1 (Scc1)

    TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...
  • Page 263 When enabled, the parity function inserts a parity bit in the most significant bit position. (See Figure 15-3.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 264: Sci Control Register 2

    – Enables the TC bit to generate transmitter CPU interrupt requests – Enables the SCRF bit to generate receiver CPU interrupt requests – Enables the IDLE bit to generate receiver CPU interrupt requests Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 265: Sci Control Register 2 (Scc2)

    This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 266 RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 267: Sci Control Register 3

    Address: $0015 Bit 7 Bit 0 Read: ORIE NEIE FEIE PEIE Write: Reset: = Unimplemented R = Reserved U = Unaffected Figure 15-11. SCI Control Register 3 (SCC3) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)
  • Page 268 15.9.4 SCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 269: Sci Status Register 1

    SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 270 This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI)
  • Page 271 SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 272: Flag Clearing Sequence

    PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 273: Sci Status Register 2

    Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 274: Sci Data Register

    R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register. NOTE: Do not use read/modify/write instructions on the SCI data register. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 275: Sci Baud Rate Register

    SCP1 and SCP0 Prescaler Divisor (PD) SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 15-7. Reset clears SCR2–SCR0. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)

  • Page 276: Sci Baud Rate Selection

    This makes the formula: CGMXCLK baud rate ----------------------------------- - × × 64 PD BD Table 15-8 shows the SCI baud rates that can be generated with a 4.9152MHz CGMXCLK. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 277: Sci Baud Rate Selection Examples

    Divisor (PD) and SCR0 Divisor (BD) (CGMXCLK=4.9152 MHz) 76,800 38,400 19,200 9600 4800 2400 1200 25,600 12,800 6400 3200 1600 19,200 9600 4800 2400 1200 5908 2954 1477 MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Communications Interface Module (SCI)
  • Page 278 Serial Communications Interface Technical Data MC68HC908AB32 Rev. 1.0 — Serial Communications Interface Module (SCI) MOTOROLA...

  • Page 279: Contents

    Technical Data — MC68HC908AB32 Section 16. Serial Peripheral Interface Module (SPI) 16.1 Contents 16.2 Introduction ........280 16.3...

  • Page 280: Introduction

    Overflow error flag with CPU interrupt capability • Programmable wired-OR mode • C (inter-integrated circuit) compatibility • I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 281: Pin Name Conventions And I/O Register Addresses

    SPI Status and Control $0011 Write: Register (SPSCR) Reset: Read: SPI Data Register $0012 Write: (SPDR) Reset: Unaffected by reset = Unimplemented = Reserved Figure 16-1. SPI I/O Register Summary MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Peripheral Interface Module (SPI)

  • Page 282: Spi Module Block Diagram

    MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt- driven. The following paragraphs describe the operation of the SPI module. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 283: Master Mode

    MOSI pin under the control of the serial clock. (See Figure 16-3.) MASTER MCU SLAVE MCU MISO MISO SHIFT REGISTER MOSI MOSI SHIFT REGISTER SPSCK SPSCK BAUD RATE GENERATOR Figure 16-3. Full-Duplex Master-Slave Connections MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Peripheral Interface Module (SPI)

  • Page 284: Slave Mode

    SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI)

  • Page 285: Transmission Formats

    SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 286: Transmission Format When Cpha = 0

    The slave’s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 16-5. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 287: Transmission Format (Cpha = 0)

    SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 288: Transmission Format When Cpha = 1

    FROM MASTER MISO BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 FROM SLAVE TO SLAVE CAPTURE STROBE Figure 16-6. Transmission Format (CPHA = 1) Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 289: Transmission Initiation Latency

    SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 290: Transmission Start Delay (Master)

    EARLIEST LATEST 32 POSSIBLE START POINTS WRITE TO SPDR CLOCK SPSCK = INTERNAL CLOCK ÷ 128; EARLIEST LATEST 128 POSSIBLE START POINTS Figure 16-7. Transmission Start Delay (Master) Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 291: Queuing Transmission Data

    Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 292: Error Conditions

    SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI)

  • Page 293: Missed Read Of Overflow Condition

    SPRF bit. Figure 16-10 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Peripheral Interface Module (SPI)

  • Page 294: Mode Fault Error

    For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI)
  • Page 295 When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 296: Interrupts

    SPI receiver CPU interrupt request Receiver full (SPRIE = 1) OVRF SPI receiver/error interrupt request (ERRIE = 1) Overflow MODF SPI receiver/error interrupt request (ERRIE = 1) Mode fault Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 297: Spi Interrupt Request Generation

    CPU interrupt requests. NOT AVAILABLE SPTE SPTIE SPI TRANSMITTER CPU INTERRUPT REQUEST NOT AVAILABLE SPRIE SPRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF Figure 16-11. SPI Interrupt Request Generation MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Peripheral Interface Module (SPI)

  • Page 298: Resetting The Spi

    By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI)

  • Page 299: Low-Power Modes

    The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 300: Spi During Break Interrupts

    MISO — Data received • MOSI — Data transmitted • SPSCK — Serial clock • SS — Slave select • CGND — Clock ground (internally connected to V Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 301: Miso (Master In/Slave Out)

    MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 302: Spsck (Serial Clock)

    A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high- impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI)

  • Page 303: Cgnd (Clock Ground)

    CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is internally connected to V shown in Table 16-1. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Serial Peripheral Interface Module (SPI)

  • Page 304: I/O Registers

    SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...
  • Page 305 SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 306: Spi Status And Control Register

    SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...
  • Page 307 During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 308: Spi Master Baud Rate Selection

    Use this formula to calculate the SPI baud rate: CGMOUT Baud rate ------------------------- - × 2 BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 309: Spi Data Register

    Figure 16-15. SPI Data Register (SPDR) R7–R0/T7–T0 — Receive/Transmit Data Bits NOTE: Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...
  • Page 310 Serial Peripheral Interface Module (SPI) Technical Data MC68HC908AB32 Rev. 1.0 — Serial Peripheral Interface Module (SPI) MOTOROLA...

  • Page 311: Contents

    Technical Data — MC68HC908AB32 Section 17. Input/Output (I/O) Ports 17.1 Contents 17.2 Introduction ........312 17.3...

  • Page 312: Introduction

    Data Direction Register C $0006 Write: (DDRC) Reset: Read: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Data Direction Register D $0007 Write: (DDRD) Reset: Figure 17-1. I/O Port Register Summary Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...
  • Page 313 $003D Register Write: (PTDPUE) Reset: Read: Port F Input Pullup Enable PTFPUE7 PTFPUE6 PTFPUE5 PTFPUE4 PTFPUE3 PTFPUE2 PTFPUE1 PTFPUE0 $003E Register Write: (PTFPUE) Reset: Figure 17-1. I/O Port Register Summary MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 314: Port Control Register Bits Summary

    PTD1 — — — DDRD2 PTD2 DDRD3 PTD3 TBSC DDRD4 TIMB PS[2:0] PTD4/TBCLK $0040 DDRD5 — — — PTD5 TASC DDRD6 TIMA PS[2:0] PTD6/TACLK $0020 DDRD7 — — — PTD7 Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...
  • Page 315 $0045 TBSC1 DDRF5 ELS1B:ELS1A PTF5/TBCH1 $0048 DDRF6 PTF6 — — — DDRF7 PTF7 DDRG0 KBIE0 PTG0/KBD0 DDRG1 KBIE1 PTG1/KBD1 KBIER DDRG2 KBIE2 PTG2/KBD2 $0021 DDRH0 KBIE3 PTH0/KBD3 DDRH1 KBIE4 PTH1/KBD4 MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 316: Port A

    A pin; a logic 0 disables the output buffer. Address: $0004 Bit 7 Bit 0 Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: Figure 17-3. Data Direction Register A (DDRA) Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 317: Port A I/O Circuit

    Write Input, Hi-Z DDRA[7:0] PTA[7:0] Output DDRA[7:0] PTA[7:0] PTA[7:0] Notes: 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 318: Port B

    PTBx/ATDx pin, while PTB is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports. Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports...

  • Page 319: Data Direction Register B (Ddrb)

    B I/O logic. READ DDRB ($0005) WRITE DDRB ($0005) DDRBx RESET WRITE PTB ($0001) PTBx PTBx READ PTB ($0001) To Analog-To-Digital Converter Figure 17-7. Port B I/O Circuit MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 320: Port C

    The port C data register contains a data latch for each of the six port C pins. Address: $0002 Bit 7 Bit 0 Read: PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Write: Reset: Unaffected by reset Alternative Function: MCLK Figure 17-8. Port C Data Register (PTC) Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 321: Data Direction Register C (Ddrc)

    Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 17-10 shows the port C I/O logic. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 322: Port C I/O Circuit

    Input, Hi-Z DDRC[5:0] PTC[5:0] Output DDRC[5:0] PTC[5:0] PTC[5:0] Notes: 1. X = don’t care; except PTC2. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 323: Port D

    TBCLK — Timer B Clock Input The PTD4 pin becomes TBCLK, the timer B (TIMB) external clock input when the TIMB prescaler select bits, PS[2:0] = 111. See Section 12. Timer Interface Module B (TIMB). MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 324: Data Direction Register D (Ddrd)

    PTDPUEx WRITE DDRD ($0007) DDRDx RESET WRITE PTD ($0003) PTDx PTDx READ PTD ($0003) PTD6 to TACLK of TIMA PTD4 to TBCLK of TIMB Figure 17-13. Port D I/O Circuit Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 325: Port D Input Pullup Enable Register (Ptdpue)

    These writable bits are software programmable to enable pullup devices on an input port pin. 1 = Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin internal pullup disconnected MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 326: Port E

    The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTE6/MOSI pin is available for general-purpose I /O. See 16.14.1 SPI Control Register. Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...
  • Page 327 E pins that are being used by the SPI module, TIMA, and SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 17-6. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 328: Data Direction Register E (Ddre)

    Figure 17-17 shows the port E I/O logic. READ DDRE ($000C) WRITE DDRE ($000C) DDREx RESET WRITE PTE ($0008) PTEx PTEx READ PTE ($0008) Figure 17-17. Port E I/O Circuit Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 329: Port F

    TBCH0 TBCH3 TBCH2 TACH3 TACH2 Additional Function: Input pullup Input pullup Input pullup Input pullup Input pullup Input pullup Input pullup Input pullup Figure 17-18. Port F Data Register (PTF) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 330: Data Direction Register F (Ddrf)

    These read/write bits control port F data direction. Reset clears DDRF[7:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 331: Port F I/O Circuit

    Input, Hi-Z DDRF[7:0] PTF[7:0] Output DDRF[7:0] PTF[7:0] PTF[7:0] Notes: 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 332: Port F Input Pullup Enable Register (Ptfpue)

    Port G is a 3-bit special-function port that shares all three of its pins with the keyboard interrupt (KBI) module. 17.9.1 Port G Data Register (PTG) The port G data register (PTG) contains a data latch for each of the three port G pins. Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 333: Data Direction Register G (Ddrg)

    G pin; a logic 0 disables the output buffer. Address: $000E Bit 7 Bit 0 Read: DDRG2 DDRG1 DDRG0 Write: Reset: Figure 17-23. Data Direction Register G (DDRG) MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...

  • Page 334: Port G I/O Circuit

    Input, Hi-Z DDRG[2:0] PTG[2:0] Output DDRG[2:0] PTG[2:0] PTG[2:0] Notes: 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 335: Port H

    Data direction register H determines whether each port H pin is an input or an output. Writing logic 1 to a DDRH bit enables the output buffer for the corresponding port H pin; a logic 0 disables the output buffer. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 336: Data Direction Register H (Ddrh)

    The data latch can always be written, regardless of the state of its data direction bit. Table 17-6 summarizes the operation of the port H pins. Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 337: Port H Pin Functions

    Input, Hi-Z DDRH[1:0] PTH[1:0] Output DDRH[1:0] PTH[1:0] PTH[1:0] Notes: 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Input/Output (I/O) Ports...
  • Page 338 Input/Output (I/O) Ports Technical Data MC68HC908AB32 Rev. 1.0 — Input/Output (I/O) Ports MOTOROLA...

  • Page 339: Contents

    Technical Data — MC68HC908AB32 Section 18. External Interrupt (IRQ) 18.1 Contents 18.2 Introduction ........339 18.3...

  • Page 340: Functional Description

    When set, the IMASK bit in the ISCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. Technical Data MC68HC908AB32 Rev. 1.0 — External Interrupt (IRQ)

  • Page 341: Irq Module Block Diagram

    Figure 18-1. IRQ Module Block Diagram Addr. Register Name Bit 7 Bit 0 Read: IRQF IRQ Status and Control IMASK MODE $001A Register Write: (ISCR) Reset: = Unimplemented Figure 18-2. IRQ I/O Register Summary MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA External Interrupt (IRQ)

  • Page 342: Irq Pin

    Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. Technical Data MC68HC908AB32 Rev. 1.0 — External Interrupt (IRQ) MOTOROLA...

  • Page 343: Irq Status And Control Register (Iscr)

    This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 344: Irq Module During Break Interrupts

    With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. Technical Data MC68HC908AB32 Rev. 1.0 — External Interrupt (IRQ)

  • Page 345: Contents

    Technical Data — MC68HC908AB32 Section 19. Keyboard Interrupt Module (KBI) 19.1 Contents 19.2 Introduction ........345 19.3...

  • Page 346: Features

    Pin Selected for KBI Function by Full MCU Pin Name Generic Pin Name KBIEx Bit in KBIER KBD0 PTG0/KBD0 KBIE0 KBD1 PTG1/KBD1 KBIE1 KBD2 PTG2/KBD2 KBIE2 KBD3 PTH0/KBD3 KBIE3 KBD4 PTH1/KBD4 KBIE4 Technical Data MC68HC908AB32 Rev. 1.0 — Keyboard Interrupt Module (KBI) MOTOROLA...

  • Page 347: Functional Description

    If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 348 However, the data direction register bit must be a logic 0 for software to read the pin. Technical Data MC68HC908AB32 Rev. 1.0 — Keyboard Interrupt Module (KBI) MOTOROLA...

  • Page 349: Keyboard Initialization

    19.5.2 Keyboard Status and Control Register • Flags keyboard interrupt requests. • Acknowledges keyboard interrupt requests. • Masks keyboard interrupt requests. • Controls keyboard interrupt triggering sensitivity. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Keyboard Interrupt Module (KBI)

  • Page 350: Keyboard Status And Control Register (Kbscr)

    This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only Technical Data MC68HC908AB32 Rev. 1.0 — Keyboard Interrupt Module (KBI) MOTOROLA...

  • Page 351: Keyboard Interrupt Enable Register

    19.7 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 352: Keyboard Module During Break Interrupts

    With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. Technical Data MC68HC908AB32 Rev. 1.0 — Keyboard Interrupt Module (KBI)

  • Page 353: Section 20. Computer Operating Properly (Cop)

    Technical Data — MC68HC908AB32 Section 20. Computer Operating Properly (COP) 20.1 Contents 20.2 Introduction ........353 20.3...

  • Page 354: Functional Description

    5 of the prescaler. NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. Technical Data MC68HC908AB32 Rev. 1.0 — Computer Operating Properly (COP) MOTOROLA...

  • Page 355: I/O Signals

    Reading the COP control register returns the low byte of the reset vector. 20.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 356: Internal Reset

    0 = COP timeout period is 2 – 2 CGMXCLK cycles COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled Technical Data MC68HC908AB32 Rev. 1.0 — Computer Operating Properly (COP) MOTOROLA...

  • Page 357: Cop Control Register

    IRQ pin, the COP is automatically disabled until a POR occurs. 20.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Computer Operating Properly (COP)

  • Page 358: Wait Mode

    STOP instruction results in an illegal opcode reset. 20.9 COP Module During Break Mode The COP is disabled during a break interrupt when V is present on the RST pin. Technical Data MC68HC908AB32 Rev. 1.0 — Computer Operating Properly (COP) MOTOROLA...

  • Page 359: Contents

    Technical Data — MC68HC908AB32 Section 21. Low-Voltage Inhibit (LVI) 21.1 Contents 21.2 Introduction ........359 21.3...

  • Page 360: Functional Description

    STOP INSTRUCTION LVISTOP FROM CONFIG1 FROM CONFIG1 LVIRSTD LVIPWRD FROM CONFIG1 > LVI LVI RESET LOW V Trip DETECTOR ≤ LVI Trip LVIOUT TO LVISR Figure 21-1. LVI Module Block Diagram Technical Data MC68HC908AB32 Rev. 1.0 — Low-Voltage Inhibit (LVI) MOTOROLA...

  • Page 361: Polled Lvi Operation

    LVI level for 9 or more consecutive CPU TRIPF cycles. V must be above LVI for only one CPU cycle to bring the TRIPR MCU out of reset. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Low-Voltage Inhibit (LVI)

  • Page 362: Lvi Status Register (Lvisr)

    0 or 1 TRIPF < LVI > 40 CGMXCLK cycles TRIPF < V < LVI Previous value TRIPF TRIPR 21.6 LVI Interrupts The LVI module does not generate interrupt requests. Technical Data MC68HC908AB32 Rev. 1.0 — Low-Voltage Inhibit (LVI) MOTOROLA...

  • Page 363: Low-Power Modes

    If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 364 Low-Voltage Inhibit (LVI) Technical Data MC68HC908AB32 Rev. 1.0 — Low-Voltage Inhibit (LVI) MOTOROLA...

  • Page 365: Contents

    Technical Data — MC68HC908AB32 Section 22. Break Module (BRK) 22.1 Contents 22.2 Introduction ........365 22.3...

  • Page 366: Features

    A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 22-1 shows the structure of the break module. Technical Data MC68HC908AB32 Rev. 1.0 — Break Module (BRK) MOTOROLA...

  • Page 367: Break Module Block Diagram

    Read: BRKE BRKA Break Status and Control $FE0E Write: Register (BRKSCR) Reset: = Unimplemented = Reserved Note: Writing a logic 0 clears SBSW. Figure 22-2. Break Module I/O Register Summary MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Break Module (BRK)

  • Page 368: Flag Protection During Break Interrupts

    SBSW is set (see Section 8. System Integration Module (SIM)). Clear the SBSW bit by writing logic 0 to it. Technical Data MC68HC908AB32 Rev. 1.0 — Break Module (BRK) MOTOROLA...

  • Page 369: Stop Mode

    This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 370: Break Address Registers

    The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. Technical Data MC68HC908AB32 Rev. 1.0 — Break Module (BRK)

  • Page 371: Sim Break Status Register (Sbsr)

    LOBYTE,SP ;If RETURNLO is not zero, DOLO ;then just decrement low byte. HIBYTE,SP ;Else deal with high byte, too. DOLO LOBYTE,SP ;Point to WAIT/STOP opcode. RETURN PULH ;Restore H register. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Break Module (BRK)

  • Page 372: Sim Break Flag Control Register

    MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Technical Data MC68HC908AB32 Rev. 1.0 — Break Module (BRK) MOTOROLA...

  • Page 373: Introduction

    Technical Data — MC68HC908AB32 Section 23. Electrical Specifications 23.1 Contents 23.2 Introduction ........373 23.3...

  • Page 374: Absolute Maximum Ratings

    ≤ (V ) ≤ V range V or V . Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either V or V Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 375: Functional Operating Range

    2. K is a constant unique to the device. K can be determined for a known T and measured . With this value of K, P and T can be determined for any value of T MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA...

  • Page 376: V Dc Electrical Characteristics

    C Out Capacitance — — Ports (as input or output) C In — — + 2.5 Monitor mode entry voltage — Low-voltage inhibit, trip falling voltage – target — 4.11 — LVII Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 377: Eeprom And Memory Characteristics

    — Years Notes: 1. Programming a byte more times than the specified maximum may affect the data integrity of that byte. The byte must be erased before it can be programmed again. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Electrical Specifications...

  • Page 378: V Control Timing

    TBD t 23.9 Timer Interface Module Characteristics Characteristic Symbol Unit t TIH , t TIL Input capture pulse width — t TCH , t TCL (1/f Input clock pulse width — Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 379: Adc Characteristics

    2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. 3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 4. The external system error caused by input leakage current is approximately equal to the product of R source and input current. MC68HC908AB32 Rev. 1.0 Technical Data —...

  • Page 380: Spi Characteristics

    , unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 381: Spi Master Timing

    MASTER LSB OUT OUTPUT Note: This last clock edge is generated internally, but is not seen at the SPSCK pin. b) SPI Master Timing (CPHA = 1) Figure 23-1. SPI Master Timing MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Electrical Specifications...

  • Page 382: Spi Slave Timing

    OUTPUT MOSI BITS 6–1 MSB IN LSB IN INPUT Note: Not defined but normally LSB of character previously transmitted b) SPI Slave Timing (CPHA = 1) Figure 23-2. SPI Slave Timing Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 383: Clock Generation Module Characteristics

    Capacitor Pin Fact XCLK) (CGMXFC). must provide low AC impedance from f = /100 to 100 × 0.1 µF XCLK Bypass capacitor — — , so series VCLK resistance must be considered. MC68HC908AB32 Rev. 1.0 Technical Data — MOTOROLA Electrical Specifications...

  • Page 384: Cgm Acquisition/Lock Time Information

    × (N/4) over 2 ms (GBNT) Notes: ± 1. V = 5.0 Vdc 10%, V = 0 Vdc, T to T , unless otherwise noted. 2. GBNT guaranteed but not tested. Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 385: Flash Memory Characteristics

    7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. MC68HC908AB32 Rev. 1.0 Technical Data —...
  • Page 386 Electrical Specifications Technical Data MC68HC908AB32 Rev. 1.0 — Electrical Specifications MOTOROLA...

  • Page 387: Contents

    Technical Data — MC68HC908AB32 Section 24. Mechanical Specifications 24.1 Contents 24.2 Introduction ........387 24.3...

  • Page 388: 64-Pin Plastic Quad Flat Pack (Qfp)

    CANNOT BE LOCATED ON THE LOWER RADIUS 0° — 0° — DETAIL C OR THE FOOT. 16.95 17.45 0.667 0.687 0.35 0.45 0.014 0.018 1.6 REF 0.063 REF Figure 24-1. 64-Pin Plastic Quad Flat Pack (QFP) Technical Data MC68HC908AB32 Rev. 1.0 — Mechanical Specifications MOTOROLA...

  • Page 389: Section 25. Ordering Information

    MC Order Numbers ....... . 389 25.2 Introduction This section contains ordering numbers for the MC68HC908AB32. 25.3 MC Order Numbers Table 25-1.
  • Page 390 Ordering Information Technical Data MC68HC908AB32 Rev. 1.0 — Ordering Information MOTOROLA...
  • Page 392 Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

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