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Timer Interface Module B (TIMB)
12.10.5 TIMB Channel Registers
Technical Data
218
OVERFLOW
PERIOD
TBCHx
OUTPUT
COMPARE
CHxMAX
Figure 12-13. CHxMAX Latency
These read/write registers contain the captured TIMB counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMB channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIMB channel x registers (TBCHxH) inhibits output compares until
the low byte (TBCHxL) is written.
Address:
$0046
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
Figure 12-14. TIMB Channel 0 Register High (TBCH0H)
Address:
$0047
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
Figure 12-15. TIMB Channel 0 Register Low (TBCH0L)
Timer Interface Module B (TIMB)
OVERFLOW
OVERFLOW
OUTPUT
OUTPUT
COMPARE
COMPARE
5
4
3
13
12
11
Indeterminate after reset
5
4
3
5
4
3
Indeterminate after reset
OVERFLOW
OVERFLOW
OUTPUT
COMPARE
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
2
1
Bit 0
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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