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MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Address:
$002C
Bit 7
6
Read:
CH2F
CH2IE
Write:
0
Reset:
0
0
Figure 11-11. TIMA Channel 2 Status and Control Register (TASC2)
Address:
$002F
Bit 7
6
Read:
CH3F
CH3IE
Write:
0
Reset:
0
0
Figure 11-12. TIMA Channel 3 Status and Control Register (TASC3)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIMA channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Timer Interface Module A (TIMA)
5
4
3
MS2B
MS2A
ELS2B
0
0
0
5
4
3
0
MS3A
ELS3B
0
0
0
Timer Interface Module A (TIMA)
I/O Registers
2
1
ELS2A
TOV2
0
0
2
1
ELS3A
TOV3
0
0
Technical Data
Bit 0
CH2MAX
0
Bit 0
CH3MAX
0
189
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