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Timer Interface Module B (TIMB)
Addr.
Register Name
Timer B Channel 1
$004A
Register Low
(TBCH1L)
Timer B Channel 2 Status
$0032
and Control Register
(TBSC2)
Timer B Channel 2
$0033
Register High
(TBCH2H)
Timer B Channel 2
$0034
Register Low
(TBCH2L)
Timer B Channel 3 Status
$0035
and Control Register
(TBSC3)
Timer B Channel 3
$0036
Register High
(TBCH3H)
Timer B Channel 3
$0037
Register Low
(TBCH3L)
Figure 12-2. TIMB I/O Register Summary (Sheet 2 of 2)
12.5.2 Input Capture
Technical Data
200
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
Read:
CH2F
CH2IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
Read:
Bit 7
6
Write:
Reset:
Read:
CH3F
CH3IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
Read:
Bit 7
6
Write:
Reset:
= Unimplemented
With the input capture function, the TIMB can capture the time at which
an external event occurs. When an active edge occurs on the pin of an
input capture channel, the TIMB latches the contents of the TIMB
counter into the TIMB channel registers, TBCHxH:TBCHxL. The polarity
of the active edge is programmable. Input captures can generate
TIMB CPU interrupt requests.
Timer Interface Module B (TIMB)
5
4
3
5
4
3
Indeterminate after reset
MS2B
MS2A
ELS2B
0
0
0
13
12
11
Indeterminate after reset
5
4
3
Indeterminate after reset
0
MS3A
ELS3B
0
0
0
13
12
11
Indeterminate after reset
5
4
3
Indeterminate after reset
2
1
Bit 0
2
1
Bit 0
ELS2A
TOV2
CH2MAX
0
0
0
10
9
Bit 8
2
1
Bit 0
ELS3A
TOV3
CH3MAX
0
0
0
10
9
Bit 8
2
1
Bit 0
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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