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Controller
MC68824
User manual
Motorola MC68824 User Manual
Token-passing bus controller
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
List of Illustrations
Features
Introduction
150/051 Reference Model
IEEE 802.4 Token Bus Local Area Networks
IEEE Local Area Network Standards
Token Bus Operation
Options Within IEEE
Microprocessor System Bus Interface
Physical Layer Interface
Token Bus LAN Node
Shared Memory
Overview of TBC Functional Operation
Command Structure Overview
Frame Reception Overview
Frame Transmission Overview
Tables 2.1 TBC Private Area
Next Station Address
Data Organization in Memory
TBC Private Area
Previous Station Address
Last Token-Rotation-Time
Token Rotation Time at Start of Access Classes
Target Token Rotation Time for Access Classes
Token Rotation Time at Start of Ring Maintenance
Target Rotation Time for Ring Maintenance
Ring Maintenance Time Initial Value
Source Routing - Source Segment/Bridge 10 (SID)
Source Routing - Target Segment/Bridge 10 (TID)
Segment Number Mask for Source Routing
RX Frame Status Error Mask
TX Queue Access Class Status
TX Queue Access Class Pointers
RX Queue Access Class Pointers
Free Frame Descriptor Pointer
Free Buffer Descriptor Pointer
Group Address Mask
Individual Address Mask
Non-RWR Maximum Retry Limit
RWR Maximum Retry Limit
Slot Time
Manufacturer Product Revision and 802.4 Standard Revision Number
Transmitter Fault Count
Private Area Function Code
Private Area Pointer
Parameters Initializing the Private Area
Initial Pad Timer Preset (PTP)
Initial In-Ring Desired
Initial Address Length
Response Destination Address Pointer
Response Pointer
Request with Response Pointer
Command Parameter Area
Interrupt Status Words
Interrupt Status Word 1
Interrupt Masks
Statistics
Number of Tokens Passed
Number of Tokens Heard
Number of Passes through no Successor 8
Number of Who Follows
Number of Token Pass Failed
Number of Frames too Long (>8K Bytes)
Number of no FD/BD Errors
Number of Overruns
Modem Error Counters
Non-Silence
FCS Errors
E-Bit Errors
Frame Fragments
DMA Dump Area
Commands
Registers
TBC Register Map
Command Register (CR)
Data Register (DR)
Interrupt Vector Register (IV)
Semaphore Register
Command Parameter Area
Initialization Table
Buffer Structures
Linked Buffer Structures
TBC Queues
Frame Descriptor Format
Buffer Descriptor Format
Examples of Queues Status
Free Frame Descriptor and Buffer Descriptor Pools
MC68824 Signals
Data Strobe Control of Data Bus in Master Mode
Physical Layer Interface
Request Channel Encodings for MAC Mode (SMREQ = 1)
Indication Channel Encodings for MAC Mode (SMIND = 1)
Typical Station Management Sequence
Bus Operation
Host Processor Read Cycle with Two Wait States
Host Processor Write Cycle
Interrupt Acknowledge Cycle
Read Cycle and Slow Read Cycle
BEC Encoding Definitions
Write Cycle and Slow Write Cycle
TBC Write Cycle with HALT
TBC Read Cycle with Bus Error
TBC Read Cycle with Retry
TBC Read Cycle with Relinquish and Retry, Early and Late
Bus Arbitration
Bus Arbitration Unit State Diagram
Bus Timing Diagram
Tbcinterfaces
Electrical Specifications
Ordering Information and Mechanical Data
IEEE 802.4 Operation
Frame Formats and Addressing
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