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EEPROM
5.6 EEPROM Timebase Requirements
5.7 EEPROM Security Options
5.8 EEPROM Block Protection
Technical Data
72
A 35µs timebase is required by the EEPROM control circuit for program
and erase of EEPROM content. This timebase is derived from dividing
the CGMXCLK or bus clock (selected by EEDIVCLK bit in CONFIG2
register) using a timebase divider circuit, controlled by the 16-bit
EEPROM timebase divider register (EEDIVH and EEDIVL).
As the CGMXCLK or bus clock is user selected, the EEPROM timebase
divider register must be configured with the appropriate value to obtain
the 35µs. The timebase divider is calculated using the following formula:
Reference frequency (Hz) × 35 × 10
[
EEDIV = INT
This value is written to the EEPROM timebase divider register (EEDIVH
and EEDIVL) or programmed into the EEPROM timebase divider non-
volatile register prior to any EEPROM program or erase operations (see
5.5 EEPROM Configuration
Non-Volatile
Register).
The EEPROM has a special security option, enabled by programming
the EEPRTCT bit to 0 in the EEPROM non-volatile register (EENVR).
Once security is enabled, the following limitations apply to the EEPROM:
•
The 16-byte EEPROM locations from $08F0 to $08FF are
protected from erase and program operations.
•
The block erase and bulk erase modes are disabled. Byte erase
can be used for all EEPROM locations except $08F0 to $08FF.
•
The EENVR is protected from further erase or program
operations.
The 512 bytes of EEPROM is divided into four 128-byte blocks. Each of
these blocks can be protected from erase/program operations by setting
the EEBPx bit in the EENVR.
the blocks.
EEPROM
and
5.11.3.1 EEPROM Timebase Divider
Table 5-1
shows the address ranges for
MC68HC908AB32
–6
]
+ 0.5
Rev. 1.0
—
MOTOROLA
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