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Clock Generator Module (CGM)
9.5 I/O Signals
9.5.1 Crystal Amplifier Input Pin (OSC1)
9.5.2 Crystal Amplifier Output Pin (OSC2)
9.5.3 External Filter Capacitor Pin (CGMXFC)
NOTE:
9.5.4 PLL Analog Power Pin (V
NOTE:
9.5.5 Oscillator Enable Signal (SIMOSCEN)
Technical Data
142
The following paragraphs describe the CGM I/O signals.
The OSC1 pin is an input to the crystal oscillator amplifier.
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
To prevent noise problems, C
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C
)
DDA
V
is a power pin used by the analog portions of the PLL. The pin
DDA
should be connected to the same voltage potential as the V
Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
Clock Generator Module (CGM)
should be placed as close to the
F
connection.
F
MC68HC908AB32
pin.
DD
Rev. 1.0
—
MOTOROLA
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