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Addr.
Register Name
PIT Status and Control
$004B
Register
PIT Counter Register High
$004C
(PCNTH)
PIT Counter Register Low
$004D
(PCNTL)
PIT Counter Modulo
$004E
Register High
(PMODH)
PIT Counter Modulo
$004F
Register Low
(PMODL)
13.4.1 PIT Counter Prescaler
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Bit 7
Read:
POF
Write:
0
(PSC)
Reset:
0
Read:
Bit 15
Write:
Reset:
0
Read:
Bit 7
Write:
Reset:
0
Read:
Bit 15
Write:
Reset:
1
Read:
Bit 7
Write:
Reset:
1
= Unimplemented
Figure 13-2. PIT I/O Register Summary
The clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PPS[2:0] in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler
output determines the frequency of the Periodic Interrupt. The PIT
overflow flag (POF) is set when the PIT counter value rolls over to $0000
after matching the value in the PIT counter modulo registers. The PIT
interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests.
POF and POIE are in the PIT status and control register.
Programmable Interrupt Timer (PIT)
6
5
4
0
POIE
PSTOP
PRST
0
1
0
14
13
12
0
0
0
6
5
4
0
0
0
14
13
12
1
1
1
6
5
4
1
1
1
Programmable Interrupt Timer (PIT)
Functional Description
3
2
1
0
PPS2
PPS1
0
0
0
11
10
9
0
0
0
3
2
1
0
0
0
11
10
9
1
1
1
3
2
1
1
1
1
Technical Data
Bit 0
PPS0
0
Bit 8
0
Bit 0
0
Bit 8
1
Bit 0
1
223
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