Motorola MC68HC908AB32 Technical Data Manual page 102

Central Processor Unit (CPU)
Source
Operation
Form
EOR # opr
EOR opr
EOR opr
EOR opr ,X
Exclusive OR M with A
EOR opr ,X
EOR ,X
EOR opr ,SP
EOR opr ,SP
INC opr
INCA
INCX
Increment
INC opr ,X
INC ,X
INC opr ,SP
JMP opr
JMP opr
JMP opr ,X
Jump
JMP opr ,X
JMP ,X
JSR opr
JSR opr
JSR opr ,X
Jump to Subroutine
JSR opr ,X
JSR ,X
LDA # opr
LDA opr
LDA opr
LDA opr ,X
Load A from M
LDA opr ,X
LDA ,X
LDA opr ,SP
LDA opr ,SP
LDHX # opr
Load H:X from M
LDHX opr
LDX # opr
LDX opr
LDX opr
LDX opr ,X
Load X from M
LDX opr ,X
LDX ,X
LDX opr ,SP
LDX opr ,SP
LSL opr
LSLA
LSLX Logical Shift Left
LSL opr ,X (Same as ASL)
LSL ,X
LSL opr ,SP
Technical Data
102
Table 7-1. Instruction Set Summary (Continued)
PC ← Jump Address
PC ← (PC) + n ( n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
H:X ← (M:M + 1)
C
Central Processor Unit (CPU)
Effect on
Description
V H I N Z C
A ← (A ⊕ M)
0 – –
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
– –
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
– – – – – –
– – – – – –
A ← (M)
0 – –
0 – –
X ← (M)
0 – –
0
– –
b7 b0
CCR
IMM A8 ii
DIR B8 dd
EXT C8 hh ll
IX2 D8 ee ff
–
IX1 E8 ff
IX F8
SP1 9EE8 ff
SP2 9ED8 ee ff
DIR 3C dd
INH 4C
INH 5C
–
IX1 6C ff
IX 7C
SP1 9E6C ff
DIR BC dd
EXT CC hh ll
IX2 DC ee ff
IX1 EC ff
IX FC
DIR BD dd
EXT CD hh ll
IX2 DD ee ff
IX1 ED ff
IX FD
IMM A6 ii
DIR B6 dd
EXT C6 hh ll
IX2 D6 ee ff
–
IX1 E6 ff
IX F6
SP1 9EE6 ff
SP2 9ED6 ee ff
IMM 45 ii jj
–
DIR 55 dd
IMM AE ii
DIR BE dd
EXT CE hh ll
IX2 DE ee ff
–
IX1 EE ff
IX FE
SP1 9EEE ff
SP2 9EDE ee ff
DIR 38 dd
INH 48
INH 58
IX1 68 ff
IX 78
SP1 9E68 ff
MC68HC908AB32 Rev. 1.0
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