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Input/Output (I/O) Ports
NOTE:
Technical Data
334
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
READ PTG ($000A)
Figure 17-24. Port G I/O Circuit
When DDRGx is a logic 1, reading address $000A reads the PTGx data
latch. When DDRGx is a logic 0, reading address $000A reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-6
summarizes the operation of the port G pins.
Table 17-8. Port G Pin Functions
DDRG
PTG Bit
Bit
(1)
0
X
1
X
Notes:
1. X = don't care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Input/Output (I/O) Ports
DDRGx
PTGx
Accesses
I/O Pin
to DDRG
Mode
Read/Write
(2)
Input, Hi-Z
DDRG[2:0]
Output
DDRG[2:0]
Figure 17-24
shows
PTGx
KBI
Accesses to PTG
Read
Write
(3)
Pin
PTG[2:0]
PTG[2:0]
PTG[2:0]
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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