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System Integration Module (SIM)
OSC1
PORRST
CGMXCLK
CGMOUT
RST
IAB
8.4.2.2 Computer Operating Properly (COP) Reset
Technical Data
116
•
The RST pin is driven low during the oscillator stabilization time
•
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared
4096
32
CYCLES
CYCLES
CYCLES
Figure 8-7. POR Recovery
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, a value (any value) should be written
to location $FFFF. Writing to location $FFFF clears the COP counter and
bits 12 through 4 of the SIM counter. The SIM counter output, which
occurs at least every 2
counter. The COP should be serviced as soon as possible out of reset
to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at V
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
RST pin disables the COP module.
System Integration Module (SIM)
32
$FFFE
13
4
– 2
CGMXCLK cycles, drives the COP
$FFFF
TST
on the
TST
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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