Panasonic FP7 Series Command Reference Manual page 401

● Once the data is shifted, the pre-shift higher [n] bits of [D1] vanish. The post-shift lower [n]
bits of [D2] are padded with 0.
● The setting range of [n] is from 0 to 65535 (0 to 15 for CPU units older than Version 4.32).
When [n] is 0, no shift takes place.
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Processing
Example) When R4 to R27 is shifted three bits
Excluded Excluded 0 inserted for the number of shifted bits Excluded
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Precautions for programming
● In the case of a direct address and index modification address, specify the same device for
[D1] and [D2]. At the same time, specify [D2] to be greater than or equal to [D1].
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Flag operations
Name
SR7
SR8
(ER)
WUME-FP7CPUPGR-12
8.6 BITL (Left Shift of Multiple Devices for n Bits)
Description
To be set in the case of out-of-range in indirect access (index modification).
To be set when [D1] is larger than [D2].
To be set when [n] is greater than or equal to 16.
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