Panasonic FP7 Series Command Reference Manual page 311

Cpu unit
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Outline of operation
● This instruction multiplies the values [S1] and [S2] according to the operation unit [i].
● The calculation result is stored in the address starting with [D].
[S1] × [S2] → ([D] to [D]+1)
● The size of the area in which the operation result is stored varies depending on the operation
unit.
Operation
unit
US, SS
UL, SL
SF
DF
Processing
Example 1) Operation unit: 16 bits (US, SS)
Example 2) Operation unit: 32 bits (UL, SL)
Example 3) Operation unit: 32 bits (SF)
WUME-FP7CPUPGR-12
Calculation target data
16-bit × 16-bit
32-bit × 32-bit
32-bit × 32-bit
64-bit × 64-bit
6.3 MUL (Multiplication)
Calculation result
Stored in a two-word area that starts
32 bit
with [D]
Stored in a four-word area that starts
64 bit
with [D]
Stored in a two-word area that starts
32 bit
with [D]
Stored in a four-word area that starts
64 bit
with [D]
6-7

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