Lcd Clocking Control Register; Lcd Refresh Rate Adjustment Register; Table 8-14 Lcd Clocking Control Register Description; Table 8-15 Lcd Refresh Rate Adjustment Register Description - Motorola MC68VZ328 User Manual

Programming Model
8.3.13

LCD Clocking Control Register

The LCD clocking control (LCKCON) register is used to enable the LCD controller and control the LCD
memory cycle. The bit assignments for the register are shown in the following register display. The
settings for the bits in the register are listed in Table 8-14.
LCKCON
BIT 7
LCDON
TYPE rw
0
RESET
Table 8-14. LCD Clocking Control Register Description
Name
LCDON LCD Control—This bit enables the LCD controller. Default is
Bit 7 off.
Unused These bits are not used by the chip and may be used for tem-
Bits 6–0 porary storage. At reset these bits are cleared.
8.3.14

LCD Refresh Rate Adjustment Register

The LCD refresh rate adjustment (LRRA) register is used to fine-tune the display refresh rate by
introducing an idle interval between alternate LCD DMA and display cycles
register are shown in the following register display. The settings for the bits in the register are listed in
Table 8-15.
LRRA
BIT 15 14
TYPE
0 0
RESET
Table 8-15. LCD Refresh Rate Adjustment Register Description
Name
Reserved Reserved
Bits 15–10
8-18
LCD Clocking Control Register
6 5
rw rw
0 0
Description
LCD Refresh Rate Adjustment Register
13 12 11 10
0 0 0 0
Description
MC68VZ328 User's Manual
4 3
Unused
rw rw rw
0 0
0x00
0 = Disable the LCD controller
1 = Enable the LCD controller
See description
.
The bit assignments for the
9 8 7 6 5
RRA[9:0]
rw rw rw rw rw
0 0 1 1 1
0x00FF
0x(FF)FFFA27
2 1 BIT 0
rw rw
0 0 0
Setting
0x(FF)FFFA28
4 3 2 1 BIT 0
rw rw rw rw rw
1 1 1 1 1
Setting
These bits
are reserved
and should
be set to 0.