The Load/Store Unit - Motorola MPC823e Reference Manual

6.6 THE LOAD/STORE UNIT

The load/store unit handles all data transfers between the register file and chip internal bus.
It is implemented as an independent execution unit so that stalls in the memory pipeline do
not cause the master instruction pipeline to stall, unless there is a data dependency. The
unit is fully pipelined so that memory instructions of any size can be issued on back-to-back
cycles.
There is a 32-bit wide data path between the load/store unit and fixed-point register file.
Single-word accesses to the internal on-chip data RAM require one clock, resulting in two
clock latencies and double-word accesses require two clocks, which results in three clock
latencies. Because the internal bus is 32 bits wide, double-word transfers take two bus
accesses. The load/store unit implements all of the PowerPC load/store instructions in
hardware, including unaligned and string accesses.
The following is a list of the load/store unit's main features:
• Supports many instructions
• Two-entry load/store instruction address queue
• Pipelined operation
• Minimal load latency–2 clocks using 1 clock on-chip data RAM
• Minimal store latency–1 clock since the load/store unit ends the store execution in
2 clocks, using 1 clock on-chip data RAM.
• Load/store multiple and string instructions synchronize
• Load/store breakpoint/watchpoint detection support
Figure 6-6 illustrates a conceptual block diagram of the load/store unit and its two queues.
The address queue is a 2-entry queue shared by all load/store instructions and the
fixed-point data queue is a 2-entry, 32-bit wide queue that holds fixed-point data.
The load/store unit has a dedicated writeback bus so that loaded data received from the
internal bus is written directly back to the fixed- or floating-point register files.
MOTOROLA MPC823e REFERENCE MANUAL
The PowerPC Core
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