I/O Simulation; Hspice Models - Intel Agilex User Manual

Figure 20. Equivalent Circuit of Example 2 with Output Buffer Driving LOW

4.11. I/O Simulation

4.11.1. HSPICE Models

Intel Agilex devices provide a SPICE model which you can use to perform system-level
simulations for various configurations.
The SPICE kits provide models that support a wide variety of I/O features across
process, voltage, and temperature (PVT). Each SPICE kit contains the following
information:
• Encrypted transistor and logic cell library models
• Encrypted input or output buffer circuit models for single-ended and differential
I/O
• Single-ended and differential sample SPICE decks
• User guide describing the model usage
The HSPICE models provide options to simulate buffer behavior for following I/O
feature:
• RS OCT with and without calibration
• RT OCT with calibration
• Internal weak pull-up
• Open drain
• Bus-hold
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
34
40 Ω
Output buffer = LOW
4. Intel Agilex I/O Design Guidelines
UG-20214 | 2019.04.02
0.6 V
50 Ω
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