Clock Resources; Clock Control Features - Intel Agilex User Manual

sectors driven, which reduces the clock skew, and to reduce the distance between the
clock source and the furthest destination, which reduces both clock skew and total
clock insertion delay.

2.1.2. Clock Resources

Table 1. Programmable Clock Routing Resources for Intel Agilex Devices
Number of Resources Available
64 unidirectional programmable clock routing
at the boundary of each clock sector
For more information about the clock input pins connections, refer to the pin
connection guidelines.
Related Information
Intel Agilex Device Family Pin Connection Guidelines

2.1.3. Clock Control Features

The following figure shows the high level description of the Intel Agilex clock control
features—clock gating and clock divider. The clock from the I/O PLL output can be
gated dynamically. These clock signals along with other clock sources go to the
periphery distributed clock multiplexer (DCM). In the periphery DCM, the clock signal
can either pass straight through, be gated by the root clock gate, or be divided by the
clock divider.
The Intel Quartus Prime software routes the clock signal on the programmable clock
routing to reach each clock sector. The clock signal can be gated in each sector by the
SCLK gates. The clock enters the SCLK network followed by the row clock network,
and eventually reaches the registers in the core. The LAB registers have a built-in
functional clock enable feature, as shown in the following figure.
(1)
Core signals drive directly to programmable clock routing through clock switch multiplexers in
the clock sector instead of the periphery DCM block.
® ™
Intel Agilex Clocking and PLL User Guide
6
2. Intel Agilex Clocking and PLL Architecture and Features
Source of Clock Resource
For transceiver bank:
• Physical medium attachment (PMA) and physical coding sublayer
(PCS) TX and RX clocks per channel
• PMA and PCS TX and RX divide clocks per channel
• Hard IP core clock output signals
•
pins
REFCLK
(1)
• Core signals
For I/O bank:
•
I/O PLL counter outputs
C
•
I/O PLL counter outputs for feedback
M
• Phase aligner counter outputs
• Dynamic phase alignment (DPA) clock output
• Clock input pins
(1)
• Core signals
UG-20216 | 2019.04.02
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