Intel Agilex Lvds Serdes Transmitter; Lvds Serdes Transmitter Blocks; Serializer Bypass For Ddr And Sdr Operations - Intel Agilex User Manual

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02

5.2. Intel Agilex LVDS SERDES Transmitter

5.2.1. LVDS SERDES Transmitter Blocks

The dedicated circuitry consists of a true differential buffer, a serializer, and I/O PLLs
that you can share between the SERDES transmitter and receiver. The serializer takes
up to 10 bits wide parallel data from the FPGA fabric. It clocks the data into the load
registers, and serializes the data using shift registers that are clocked by the I/O PLL
sending the data to the differential buffer. The MSB of the parallel data is transmitted
first.
Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not
need a PLL if you bypass the serializer.
Figure 24. LVDS SERDES Transmitter
10 bits
maximum
data width
Table 13. Dedicated Circuitry and Features of the LVDS SERDES Transmitter
Dedicated Circuitry / Feature
Differential I/O buffer
SERDES
Phase-locked loops (PLLs)
Programmable V
OD
Programmable pre-emphasis

5.2.2. Serializer Bypass for DDR and SDR Operations

The I/O element (IOE) contains two data output registers that can each operate in
either DDR or SDR mode.
You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve
a serialization factor of 2 and 1, respectively.
Send Feedback
FPGA
Serializer
Fabric
10
tx_in
DIN DOUT
tx_coreclock
(load_enable, fast_clock, tx_coreclock)
3
I/O PLL
Supports 1.5 V True Differential Signaling I/O standard which is compatible with
LVDS, RSDS, and Mini-LVDS.
3 to 10-bit wide serializer
Clocks the load and shift registers
Adjusts the output voltage swing
Boosts output current
2
IOE
IOE supports SDR, DDR, or non-registered datapath
tx_inclock
Description
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
tx_out
+
–
LVDS SERDES Transmitter
SERDES Clock Domain
39