Clocking Differential Transmitters; Intel Agilex Lvds Serdes Receiver; Lvds Serdes Receiver Blocks - Intel Agilex User Manual

General purpose i/o and lvds serdes
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5.2.5. Clocking Differential Transmitters

The I/O PLL generates the load enable (
signal (the clock running at serial data rate) that clocks the load and shift registers.
You can statically set the serialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 using
the Intel Quartus
serialization factor setting.
You can configure any Intel Agilex transmitter data channel to generate a source-
synchronous transmitter clock output. This flexibility allows the placement of the
output clock near the data outputs to simplify board layout and reduce clock-to-data
skew.
Different applications often require specific clock-to-data alignments or specific data-
rate-to-clock-rate factors. You can specify these settings statically in the Intel Quartus
Prime parameter editor:
The transmitter can output a clock signal at the same rate as the data with a
maximum output clock frequency that each speed grade of the device supports.
You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on
the serialization factor.
You can set the phase of the clock in relation to the data at 0° or 180° (edge- or
center-aligned). The I/O PLLs provide additional support for other phase shifts in
45° increments.
Figure 28.
Transmitter in Clock Output Mode

5.3. Intel Agilex LVDS SERDES Receiver

5.3.1. LVDS SERDES Receiver Blocks

The receiver has a differential buffer and I/O PLLs that you can share among the
transmitter and receiver, a DPA block, a synchronizer, a data realignment block, and a
deserializer. The 1.5 V True Differential Signaling buffer can receive LVDS, mini-LVDS,
®
Intel
Agilex
General Purpose I/O and LVDS SERDES User Guide
42
®
Prime software. The load enable signal is derived from the
Transmitter Circuit
Parallel
FPGA
Fabric
I/O
PLL
5. Intel Agilex High-Speed SERDES I/O Architecture
) signal and the
load_enable
Series
fast_clock
load_enable
UG-20214 | 2019.04.02
fast_clock
Txclkout+
Txclkout–
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