Multipliers For Floating-Point Arithmetic - Intel Agilex User Manual

2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
Figure 13. Location of Pipeline Register for FP16 Operation Modes
fp32_chainin[31:0]
fp32_adder_a[31:0]
fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]
Legend:
1 - mult_pipeline_clken
2 - mult_2nd_pipeline_clken
3 - accum_pipeline_clken
4 - fp32_adder_a_chainin_pl_clken
5 - accum_2nd_pipeline_clken
6 - fp32_adder_a_chainin_2nd_pl_clken
7 - adder_accum_clken
8 - adder_input_clken
9 - adder_pl_clken
The following variable precision DSP block signals control the pipeline registers within
the variable precision DSP block:
• CLK
• ENA[2..0]
• CLR[1]
Related Information
Configurations for Input, Pipeline, and Output Registers
Provides information about restrictions on floating-point arithmetic pipeline
registers.

2.2.3. Multipliers for Floating-Point Arithmetic

A single-variable precision DSP block can perform many multiplications in parallel,
depending on the data width of the multiplier and implementation.
You can configure these two multipliers in several operational modes:
• One floating-point arithmetic single-precision multiplier
• Two floating-point arithmetic half-precision multiplier
Send Feedback
accumulate
Input
Register
Bank
Top
1
Multiplier
Bottom
Multiplier
3 5 7
4
6 8
Adder
2 8
*Pipeline 9
Register
fp32_chainout[31:0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Adder
Output
fp32_result[31:0]
Register
fp16_mult_top_invalid
Bank fp16_mult_top_inexact
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite
fp16_mult_top_zero
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite
fp16_mult_top_zero
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite
fp16_adder_zero
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
on page 67
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