As Configuration - Intel Agilex Configuration User Manual

Pin
flash_nwe
flash_noe
flash_clk
flash_nadv
flash_nreset
fpga_nconfig
pfl_reset_watchdog
pfl_watchdog_error
Related Information
Avalon Interface Specifications

3.2. AS Configuration

In AS configuration schemes, the SDM block in the Intel Agilex device controls the configuration process and interfaces. The
serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot
ROM. Then, the SDM loads the initial configuration firmware from AS x4 flash. After the configuration firmware loads, this
firmware controls the remainder of the configuration process, including I/O configuration and FPGA core configuration.
Designs including an HPS, can use the HPS to access serial flash memory after the initial configuration.
Intel ® Agilex ™ Configuration User Guide
86
Type Weak Pull-Up
Output —
Output —
Output —
Output —
Output —
Open Drain Output 10-kW Pull-Up
Resistor
Input —
Output —
3. Intel Agilex Configuration Schemes
Function
Connects to the pin of the flash memory device. When low enables
nWE
write operations to the flash memory device.
Connects to the pin of the flash memory device. When low enables
nOE
the outputs of the flash memory device during a read operation.
For burst mode. Connects to the input pin of the flash memory
CLK
device. The active edges of increment the flash memory device
CLK
internal address counter. The
flash_clk
frequency in burst mode for a single CFI flash. In dual CFI flash
pfl_clk
solution, the frequency runs at a quarter of the
flash_clk
frequency. Use this pin for burst mode only. Do not connect these pins
from the flash memory device to the host if you are not using burst mode.
For burst mode. Connects to the address valid input pin of the flash
memory device. Use this signal to latch the start address. Use this pin for
burst mode only. Do not connect these pins from the flash memory device
to the host if you are not using burst mode.
Connects to the reset pin of the flash memory device. A low signal resets
the flash memory device.
Connects to the pin of the FPGA. A low pulse resets the FPGA
nCONFIG
and initiates configuration. These pins are not available for the flash
programming option in the PFL II IP core.
A switch signal to reset the watchdog timer before the watchdog timer
times out. To reset the watchdog timer hold the signal high or low for at
least two clock cycles.
pfl_clk
When high indicates an error condition to the watchdog timer.
UG-20205 | 2019.10.09
frequency is half of the
pfl_clk
(7)
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