Intel Agilex I/O Termination; True Differential Signaling I/O Termination - Intel Agilex User Manual

UG-20214 | 2019.04.02
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3. Intel Agilex I/O Termination

3.1. 1.5 V True Differential Signaling I/O Termination
All GPIO banks have dedicated circuitry to support true differential I/O standards by
using the 1.5 V True Differential Signaling differential buffers without resistor
networks. The 1.5 V True Differential Signaling buffer is compatible with the LVDS,
RSDS, Mini-LVDS, and LVPECL standards ,and supports 100 Ω differential on-chip
termination (RD OCT).
Figure 6. 1.5 V True Differential Signaling I/O Standard Termination
Use OCT with these I/O standards to save board space and cost. OCT reduces the
number of external termination resistors usage. Refer to Intel Agilex device pin-out
files for more information on the dedicated differential transmitter and receiver pins.
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Termination
Differential Outputs
External
On-Board
Termination
Differential Outputs
OCT Receiver
(True LVDS
Output)
1.5 V True Differential Signaling
Differential Inputs
50 Ω
100 Ω
50 Ω
Differential Inputs
OCT
50 Ω
100 Ω
50 Ω
Receiver
ISO
9001:2015
Registered