Serializer - Intel Agilex User Manual

Figure 25. Serializer Bypass
This figure shows the serializer bypass path.
FPGA
Fabric
tx_in
tx_coreclock
• In SDR mode:
— The IOE data width is 1 bit.
— Registered output path requires a clock.
— Data is passed directly through the IOE.
• In DDR mode:
— The IOE data width is 2 bits.
— The GPIO IP core requires a clock.
—
tx_inclock

5.2.3. Serializer

The serializer consists of two sets of registers.
The first set of registers captures the parallel data from the core using the LVDS fast
clock. The
these capture registers once in each
After the data is captured, it is loaded into a shift register that shifts the LSB towards
the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS
output buffer. Therefore, higher order bits precede lower order bits in the output
bitstream.
Figure 26. LVDS SERDES x8 Serializer Bit Position
This figure shows the waveform specific to serialization factor of eight.
Table 14. LVDS SERDES Serializer Signals
Signal
tx_in[7:0]
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
40
Serializer
2
DIN DOUT
(load_enable, fast_clock, tx_coreclock)
3
I/O PLL
clocks the IOE register.
clock is provided alongside the LVDS fast clock, to enable
load_enable
tx_in[7:0]
76543210
fast_clock
load_enable
tx_out
X X X X X X X X
Data for serialization
5. Intel Agilex High-Speed SERDES I/O Architecture
2
IOE IOE supports SDR, DDR, or non-registered datapath
Note: Disabled blocks and signals are grayed out
period.
coreclock
abcdefgh ABCDEFGH
X X 7 6 5 4 3 2 1 0 a b c d e f g h A B C D E F
Description
UG-20214 | 2019.04.02
tx_out
+
-
LVDS SERDES Transmitter
XXXXXXXX
continued...
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