Intel Agilex Lvds Serdes Timing - Intel Agilex User Manual

Figure 38. Differential High-Speed Timing Diagram and Timing Budget
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Data
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
This example shows the RSKM calculation for Intel Agilex devices at 1 Gbps data rate
with a 200 ps board channel-to-channel skew.
• TCCS = 100 ps
• SW = 300 ps
• TUI = 1000 ps
• Total RCCS = TCCS + Board channel-to-channel skew = 100 ps + 200 ps = 300 ps
• RSKM = (TUI – SW – RCCS) / 2 = (1000 ps – 300 ps – 300 ps) / 2 = 200 ps
The non-DPA receiver works correctly if the RSKM is greater than 0 ps after deducting
transmitter jitter.

5.5. Intel Agilex LVDS SERDES Timing

Use the Intel Quartus Prime software to generate the required timing constraint to
perform proper timing analysis of the high-speed SERDES I/O in Intel Agilex devices.
Table 17. Timing Components
Timing Component
Source Synchronous Paths
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
52
TCCS
RSKM
RSKM
TCCS
The source synchronous paths are paths where clock and data signals are passed from the
transmitting devices to the receiving devices. For example:
5. Intel Agilex High-Speed SERDES I/O Architecture
Time Unit Interval (TUI)
SW
t (min) Internal t (max)
SW SW
Bit n Clock Bit n
Falling Edge
TUI
Clock Placement
SW
Description
UG-20214 | 2019.04.02
TCCS
RSKM
RSKM
TCCS
2
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