Debugging Guidelines For The Jtag Configuration Scheme - Intel Agilex Configuration User Manual

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
3.4.3.1. JTAG Multi-Device Configuration using Download Cable
Figure 52. Connection Setup for JTAG Multi Device Configuration using Download Cable
Download cable
10-pin male header
(JTAG mode)
Pin 1
Resistor values can vary between 1
Perform signal integrity to select the resistor

3.4.4. Debugging Guidelines for the JTAG Configuration Scheme

The JTAG configuration scheme overrides all other configuration schemes. The SDM is always ready to accept configuration
over JTAG unless a security feature disables the JTAG interface. JTAG is particularly useful in recovering a device that may be
in an unrecoverable state reached when trying to configure using a corrupted image.
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V
CCIO_SDM
10 kΩ 10 kΩ
Intel FPGA
V
CCIO_SDM
nSTATUS
nCONFIG
V
CCIO_SDM
CONF_DONE
MSEL[2:0]
TDI
V
CCIO_SDM
TMS
1 kΩ
GND
kΩ to 10 kΩ.
value for your setup.
V
CCIO_SDM
10 kΩ 10 kΩ
Intel FPGA
nSTATUS
nCONFIG
CONF_DONE
MSEL[2:0]
TDI
TDO
TCK TMS TCK
For JTAG configuration only:
Connect MSEL [2:0] of Intel FPGA devices to VCCIO_SDM through 4.7 k
For JTAG in conjunction with another configuration scheme:
Connect MSEL [2:0] of Intel FPGA devices based on the non-JTAG configuration scheme.
V
CCIO_SDM
10 kΩ 10 kΩ
Intel FPGA
nSTATUS
nCONFIG
CONF_DONE
MSEL[2:0]
TDI
TDO
TDO
TMS TCK
Ω external pull-up resistor.
Intel ® Agilex ™ Configuration User Guide
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