Intel Agilex Power Basics; Power Consumption; Power Estimation Basics - Intel Agilex User Manual

UG-20215 | 2019.04.02
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2. Intel Agilex Power Basics

2.1. Power Consumption

The total power consumption of an Intel Agilex device consists of the following
components:
• Static power—the power that the configured device consumes when powered up
but no user clocks are operating, excluding DC bias power of analog blocks, such
as I/O and transceiver analog circuitry.
• Dynamic power—the additional power consumption of the device due to signal
activity or toggling. Dynamic power is dependent on the operating frequency of
your design, applied voltage, and load capacitance, which depends on design
connectivity.
• Standby power—the component of active power that is independent of signal
activity or toggling. Standby power includes, but is not limited to, I/O and
transceiver DC bias power.
Intel Agilex devices minimize static and dynamic power using advanced process
optimizations. These optimizations allow Intel Agilex designs to meet specific
performance requirements with the lowest possible power.

2.2. Power Estimation Basics

The Intel power analysis features, including Early Power Estimator (EPE) and the Intel
Quartus Prime software Power Analyzer, give you the ability to estimate power
consumption from early design concept through design implementation, as shown in
the following figure.
As you provide more details about your design characteristics, estimation accuracy is
improved. Intel recommends that you switch from the EPE to the Power Analyzer in
the Intel Quartus Prime software once your design is available. The Power Analyzer
produces more accurate results because it has more detailed information about your
design, including routing and configuration information about all the resources in your
design.
The accuracy of the power model is determined on a per-power-rail basis for both the
Power Analyzer and the EPE. For most designs, the Power Analyzer and the EPE have
the following accuracies, with final power models:
• Power Analyzer—within 10% of silicon for the majority of power rails and the
highest power rails, assuming accurate inputs and toggle rates.
• EPE—within 15% of silicon for the majority of power rails and the highest power
rails, assuming accurate inputs and toggle rates. Recommended margins are
shown in the Report tab.
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