Chainout Adder - Intel Agilex User Manual

Variable precision dsp blocks
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Latency
Data Input Register
fp32_add
er_a_clke
n
1
Disable
2
Enable
≥3
Enable
≥4
Enable
Table 37.
Supported Register Configurations For FP16 Vector Three Mode
Latency
Data Input Register
accumu
fp32_ad
late_clk
der_a_c
en
lken
1
Disable
Disable
2
Enable
Enable
≥3
Enable
Enable
≥4
Enable
Enable

4.2.2. Chainout Adder

You can use the output chaining path to add results from another DSP block.
Support for certain operation modes:
Multiply-add or multiply-subtract mode
Vector one mode
Vector two mode
®
Intel
Agilex
Variable Precision DSP Blocks User Guide
72
4. Intel Agilex Variable Precision DSP Blocks Design Considerations
Adder 1st
Adder
Pipeline
2nd
Register
Pipeline
Register
fp16_mul
fp32_add
fp32_add
t_input_c
er_a_chai
er_a_chai
lken
nin_pl_cl
nin_2nd_
ken
pl_clken
Disable
Disable
Disable
Enable
Disable
Disable
Enable
Disable,
Disable,
enable
enable
Enable
Disable,
Disable,
enable
enable
Adder
Adder
1st
Pipeline
Pipeline
Registe
Registe
r
fp16_m
accum_
accum_
ult_inp
pipeline
2nd_pip
ut_clke
_clken
eline_cl
n
Disable
Disable
Disable
Enable
Disable
Disable
Enable
Disable,
Disable,
enable
enable
Enable
Disable,
Disable,
enable
enable
Multiplier
Multiplier
1st
2nd
Pipeline
Pipeline
Register
Register
mult_pipe
mult_2nd
line_clke
_pipeline
n
_clken
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Multipli
Multipli
2nd
er 1st
er 2nd
Pipeline
Pipeline
Registe
Registe
r
r
r
mult_pi
mult_2
accum_
peline_
nd_pipe
adder_c
clken
line_clk
ken
en
Disable
Disable
Disable
Disable
Disable
Disable
Disable,
Enable
enable
UG-20213 | 2019.04.02
Adder
Adder
Input
Pipeline
Register
Register
adder_inp
adder_pl_
output_cl
ut_clken
clken
Disable
Disable
Enable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Adder Input
Adder
Register
Pipeline
Registe
r
adder_i
adder_p
nput_cl
l_clken
lken
ken
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Send Feedback
Output
Register
ken
Output
Registe
r
output_
clken
Enable
Enable
Enable
Enable

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