Jtag Configuration - Intel Agilex Configuration User Manual

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09

3.4. JTAG Configuration

JTAG-chain device programming is ideal during development. JTAG-chain device configuration uses the JTAG pins to configure
the Intel Agilex FPGA directly with the
it does not require you to program an external flash memory. You can also use JTAG to reprogram if the image stored in quad
SPI memory. You can also use the JTAG configuration scheme to reprogram the quad SPI memory if the quad SPI content is
corrupted or invalid.
The Intel Quartus Prime software generates a
JTAG programmer to configure the Intel Agilex device. The Intel FPGA Download Cable II and the Intel FPGA Ethernet Cable
both can support the V
File ( ) for JTAG configuration.
.jbc
Intel Agilex devices automatically compress the configuration bitstream. You cannot disable compression in Intel Agilex
devices.
Table 31. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
Mode
Passive JTAG
Note:
The JTAG port has the highest priority and overrides the
device over JTAG even if the
Table 32. Power Rails for the Intel Agilex Device Configuration Pins
You can view the pin assignments for fixed pins in the Pin-Out File for your device. You specify SDM I/O pin functions using the Device
Device and Pin Options dialog box in the Intel Quartus Prime software.
Configuration Function
TCK
(8)
TDI
(8)
TMS
(8)
The JTAG pins can access the HPS JTAG chain in Intel Agilex SoC devices.
Send Feedback
file. Configuration using the JTAG device chain allows faster development because
.sof
containing the FPGA design information. You can use the
.sof
supply at 1.8 V. Alternatively, you can use the JamSTAPL Format File (
CCIO_SDM
Data Width (bits)
1
pin specify a different configuration scheme unless you disabled JTAG for security reasons.
MSEL
Pin Type
Fixed
Fixed
Fixed
Max Clock Rate Max Data Rate
30 MHz
pin settings. Consequently, you can configure the Intel Agilex
MSEL
Direction
Input
Input
Input
with a
.sof
) or Jam Byte Code
.jam
MSEL[2:0]
30 Mb 3'b111
Configuration
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V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
continued...
Intel ® Agilex ™ Configuration User Guide
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